From patchwork Wed Apr 13 12:25:40 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Wilson X-Patchwork-Id: 703671 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id p3DCQ6eE003601 for ; Wed, 13 Apr 2011 12:26:26 GMT Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id EA6B59F043 for ; Wed, 13 Apr 2011 05:26:05 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from fireflyinternet.com (server109-228-6-236.live-servers.net [109.228.6.236]) by gabe.freedesktop.org (Postfix) with ESMTP id 72B5A9E949 for ; Wed, 13 Apr 2011 05:25:49 -0700 (PDT) X-Default-Received-SPF: pass (skip=forwardok (res=PASS)) x-ip-name=78.156.66.37; Received: from arrandale.alporthouse.com (unverified [78.156.66.37]) by fireflyinternet.com (Firefly Internet SMTP) with ESMTP id 31943690-1500050 for multiple; Wed, 13 Apr 2011 13:25:40 +0100 From: Chris Wilson To: intel-gfx@lists.freedesktop.org Date: Wed, 13 Apr 2011 13:25:40 +0100 Message-Id: <1302697540-27324-1-git-send-email-chris@chris-wilson.co.uk> X-Mailer: git-send-email 1.7.4.1 X-Originating-IP: 78.156.66.37 Subject: [Intel-gfx] [PATCH] drm/i915: Relinquish any fence when changing cache levels X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.11 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Wed, 13 Apr 2011 12:26:26 +0000 (UTC) This is vital to maintain our contract with the hw for not using fences on snooped memory for older chipsets. It should have no impact other than clearing the fence register (and updating the fence bookkeeping) as any future IO access (page faults or pwrite/pread) will go through the cached CPU domain for older chipsets. On SandyBridge, we incur an extra get_fence() on the rare path that we need to perform detiling through a pagefault (i.e. texture transfers). Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_gem.c | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 6ca026d..2d16a23 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -3355,6 +3355,10 @@ int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, if (ret) return ret; + ret = i915_gem_object_put_fence(obj); + if (ret) + return ret; + ret = i915_gem_gtt_bind_object(obj, cache_level); if (ret) return ret;