From patchwork Wed Apr 13 18:01:11 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Wilson X-Patchwork-Id: 705461 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id p3DI1hNg026446 for ; Wed, 13 Apr 2011 18:02:03 GMT Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 690469F30C for ; Wed, 13 Apr 2011 11:01:42 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from fireflyinternet.com (server109-228-6-236.live-servers.net [109.228.6.236]) by gabe.freedesktop.org (Postfix) with ESMTP id 0F1869E9B2 for ; Wed, 13 Apr 2011 11:01:22 -0700 (PDT) X-Default-Received-SPF: pass (skip=forwardok (res=PASS)) x-ip-name=78.156.66.37; Received: from arrandale.alporthouse.com (unverified [78.156.66.37]) by fireflyinternet.com (Firefly Internet SMTP) with ESMTP id 31975127-1500050 for multiple; Wed, 13 Apr 2011 19:01:15 +0100 From: Chris Wilson To: intel-gfx@lists.freedesktop.org Date: Wed, 13 Apr 2011 19:01:11 +0100 Message-Id: <1302717671-1914-1-git-send-email-chris@chris-wilson.co.uk> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <87bp0ahzwn.fsf@pollan.anholt.net> References: <87bp0ahzwn.fsf@pollan.anholt.net> X-Originating-IP: 78.156.66.37 Subject: [Intel-gfx] [PATCH] drm/i915: Relinquish any fence when changing cache levels X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.11 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Wed, 13 Apr 2011 18:02:03 +0000 (UTC) This is vital to maintain our contract with the hw for not using fences on snooped memory for older chipsets. It should have no impact other than clearing the fence register (and updating the fence bookkeeping) as any future IO access (page faults or pwrite/pread) will be linear and go through the cached CPU domain. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_gem.c | 10 ++++++++++ 1 files changed, 10 insertions(+), 0 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index c38b011..39c50eb 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -3358,6 +3358,16 @@ int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, if (ret) return ret; + /* Before SandyBridge, you could not use tiling or fence + * registers with snooped memory, so relinquish any fences + * currently pointing to our region in the aperture. + */ + if (INTEL_INFO(obj->base.dev)->gen < 6) { + ret = i915_gem_object_put_fence(obj); + if (ret) + return ret; + } + ret = i915_gem_gtt_bind_object(obj, cache_level); if (ret) return ret;