From patchwork Thu Apr 14 09:03:43 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Wilson X-Patchwork-Id: 706641 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id p3E95eeZ007810 for ; Thu, 14 Apr 2011 09:06:00 GMT Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9F5C39F752 for ; Thu, 14 Apr 2011 02:05:40 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from fireflyinternet.com (server109-228-6-236.live-servers.net [109.228.6.236]) by gabe.freedesktop.org (Postfix) with ESMTP id 25FA19F702 for ; Thu, 14 Apr 2011 02:03:54 -0700 (PDT) X-Default-Received-SPF: pass (skip=forwardok (res=PASS)) x-ip-name=78.156.66.37; Received: from arrandale.alporthouse.com (unverified [78.156.66.37]) by fireflyinternet.com (Firefly Internet SMTP) with ESMTP id 32027235-1500050 for multiple; Thu, 14 Apr 2011 10:03:54 +0100 From: Chris Wilson To: intel-gfx@lists.freedesktop.org Date: Thu, 14 Apr 2011 10:03:43 +0100 Message-Id: <1302771827-26112-10-git-send-email-chris@chris-wilson.co.uk> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1302771827-26112-1-git-send-email-chris@chris-wilson.co.uk> References: <1302771827-26112-1-git-send-email-chris@chris-wilson.co.uk> X-Originating-IP: 78.156.66.37 Subject: [Intel-gfx] [PATCH 09/13] drm/i915: Use the uncached domain for the display planes X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.11 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Thu, 14 Apr 2011 09:06:01 +0000 (UTC) From: Eric Anholt The simplest and common method for ensuring scanout coherency on all chipsets is to mark the scanout buffers as uncached (and for userspace to remember to flush the render cache every so often). We can improve upon this for later generations by marking scanout objects as GFDT and only flush those cachelines when required. However, we start simple. [v2: Move the set to uncached above the clflush. Otherwise, we'd skip the clflush and try to scan out data that was still sitting in the cache.] Signed-off-by: Eric Anholt Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_gem.c | 32 +++++++++++++++++++++++--------- 1 files changed, 23 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 3f1181b..ea8e7e2 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -3105,10 +3105,6 @@ i915_gem_object_set_to_display_plane(struct drm_i915_gem_object *obj, uint32_t old_read_domains; int ret; - /* If the object is currently unbound, this is a no-op. */ - if (obj->gtt_space) - return 0; - ret = i915_gem_object_flush_gpu_write_domain(obj); if (ret) return ret; @@ -3120,14 +3116,32 @@ i915_gem_object_set_to_display_plane(struct drm_i915_gem_object *obj, return ret; } + /* The display engine is not coherent with the LLC cache on gen6. As + * a result, we make sure that the pinning that is about to occur is + * done with uncached PTEs. This is lowest common denominator for all + * chipsets. + * + * However for gen6+, we could do better by using the GFDT bit instead + * of uncaching, which would allow us to flush all the LLC-cached data + * with that bit in the PTE to main memory with just one PIPE_CONTROL. + */ + ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE); + if (ret) + return ret; + i915_gem_object_flush_cpu_write_domain(obj); - old_read_domains = obj->base.read_domains; - obj->base.read_domains |= I915_GEM_DOMAIN_GTT; + /* If the object is not bound, it will be moved into the GTT domain + * when pinned otherwise do so here. + */ + if (obj->gtt_space) { + old_read_domains = obj->base.read_domains; + obj->base.read_domains |= I915_GEM_DOMAIN_GTT; - trace_i915_gem_object_change_domain(obj, - old_read_domains, - obj->base.write_domain); + trace_i915_gem_object_change_domain(obj, + old_read_domains, + obj->base.write_domain); + } return 0; }