From patchwork Thu Apr 14 09:03:46 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Wilson X-Patchwork-Id: 706701 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id p3E98NaK009151 for ; Thu, 14 Apr 2011 09:08:43 GMT Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E548E9F76D for ; Thu, 14 Apr 2011 02:08:22 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from fireflyinternet.com (server109-228-6-236.live-servers.net [109.228.6.236]) by gabe.freedesktop.org (Postfix) with ESMTP id ACECF9E98F for ; Thu, 14 Apr 2011 02:04:01 -0700 (PDT) X-Default-Received-SPF: pass (skip=forwardok (res=PASS)) x-ip-name=78.156.66.37; Received: from arrandale.alporthouse.com (unverified [78.156.66.37]) by fireflyinternet.com (Firefly Internet SMTP) with ESMTP id 32027241-1500050 for multiple; Thu, 14 Apr 2011 10:03:55 +0100 From: Chris Wilson To: intel-gfx@lists.freedesktop.org Date: Thu, 14 Apr 2011 10:03:46 +0100 Message-Id: <1302771827-26112-13-git-send-email-chris@chris-wilson.co.uk> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1302771827-26112-1-git-send-email-chris@chris-wilson.co.uk> References: <1302771827-26112-1-git-send-email-chris@chris-wilson.co.uk> X-Originating-IP: 78.156.66.37 Subject: [Intel-gfx] [PATCH 12/13] drm/i915: Prevent mixing of snooped and tiling modes for old chipsets X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.11 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Thu, 14 Apr 2011 09:08:43 +0000 (UTC) Older chipsets do not support snooping (i.e. cache sharing between the CPU and GPU) on tiled surfaces. So prevent userspace from being silly should we one day expose the ability to change cache levels from userspace. It does enforce a strict ordering for mode changing though. So in order to change a buffer to snooped, the driver has to clear any tiling first and then change the cache level. This is consistent with how we flush and update the PTEs and seems a reasonable imposition on the driver. Deferring the check until use, whilst providing flexibilty here, implies forcing extra unbinds and a more complicated error message from, for example, execbuffer. Signed-off-by: Chris Wilson Reviewed-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_gem.c | 8 ++++++++ drivers/gpu/drm/i915/i915_gem_tiling.c | 9 +++++++++ 2 files changed, 17 insertions(+), 0 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 1f57f99..46b63c3 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -3053,6 +3053,14 @@ int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, if (obj->cache_level == cache_level) return 0; + if (INTEL_INFO(obj->base.dev)->gen < 6 && + obj->tiling_mode != I915_TILING_NONE && + cache_level != I915_CACHE_NONE) { + DRM_DEBUG("can not enable snooping on a tiled surface, " + "it must be linear for pre-SandyBridge chipsets\n"); + return -EINVAL; + } + if (obj->pin_count) { DRM_DEBUG("can not change the cache level of pinned objects\n"); return -EBUSY; diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c index 281ad3d..ca69fd4 100644 --- a/drivers/gpu/drm/i915/i915_gem_tiling.c +++ b/drivers/gpu/drm/i915/i915_gem_tiling.c @@ -331,6 +331,14 @@ i915_gem_set_tiling(struct drm_device *dev, void *data, } mutex_lock(&dev->struct_mutex); + if (INTEL_INFO(dev)->gen < 6 && + args->tiling_mode != I915_TILING_NONE && + obj->cache_level != I915_CACHE_NONE) { + DRM_DEBUG("can't not set a tiling mode on snooped memory," + "it must be linear for pre-SandyBridge chipsets\n"); + ret = -EINVAL; + goto err; + } if (args->tiling_mode != obj->tiling_mode || args->stride != obj->stride) { /* We need to rebind the object if its current allocation @@ -360,6 +368,7 @@ i915_gem_set_tiling(struct drm_device *dev, void *data, } } /* we have to maintain this existing ABI... */ +err: args->stride = obj->stride; args->tiling_mode = obj->tiling_mode; drm_gem_object_unreference(&obj->base);