From patchwork Sun Apr 17 09:32:41 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Wilson X-Patchwork-Id: 713381 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id p3H9X3Qe026702 for ; Sun, 17 Apr 2011 09:33:24 GMT Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 766729E7A8 for ; Sun, 17 Apr 2011 02:33:03 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id CBB379E78F for ; Sun, 17 Apr 2011 02:32:45 -0700 (PDT) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga101.jf.intel.com with ESMTP; 17 Apr 2011 02:32:45 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.64,226,1301900400"; d="scan'208";a="734577215" Received: from unknown (HELO cantiga.alporthouse.com) ([10.255.12.206]) by orsmga001.jf.intel.com with ESMTP; 17 Apr 2011 02:32:44 -0700 From: Chris Wilson To: intel-gfx@lists.freedesktop.org Date: Sun, 17 Apr 2011 10:32:41 +0100 Message-Id: <1303032761-2991-1-git-send-email-chris@chris-wilson.co.uk> X-Mailer: git-send-email 1.7.4.4 In-Reply-To: <1302978004-9265-1-git-send-email-chris@chris-wilson.co.uk> References: <1302978004-9265-1-git-send-email-chris@chris-wilson.co.uk> Subject: [Intel-gfx] [PATCH] drm/i915: Check that the plane points to the pipe's framebuffer before enabling X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.11 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Sun, 17 Apr 2011 09:33:24 +0000 (UTC) Knut Petersen reported a GPU hang when he left x11perf running overnight. The error state quite clearly indicates that plane A was enabled without being fully setup: PGTBL_ER: 0x00000010 Display A: Invalid GTT PTE Plane [0]: CNTR: c1000000 STRIDE: 00000c80 SIZE: 03ff04ff POS: 00000000 ADDR: 00000000 [That GTT offset on his system being pinned for the ringbuffer.] This is a simple debugging patch to assert that this cannot be so! References: https://bugs.freedesktop.org/show_bug.cgi?id=36246 Signed-off-by: Chris Wilson Cc: Jesse Barnes --- v2: Remember that gen4 splits the base + offset between different regs... --- drivers/gpu/drm/i915/intel_display.c | 29 +++++++++++++++++++++++++++++ 1 files changed, 29 insertions(+), 0 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 7734d1e..ab80046 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1274,6 +1274,34 @@ static void intel_disable_pipe(struct drm_i915_private *dev_priv, intel_wait_for_pipe_off(dev_priv->dev, pipe); } +/* Check that the DSPADDR points to the right framebufffer for the pipe. */ +static void assert_fb_bound_to_plane(struct drm_i915_private *dev_priv, + enum pipe pipe, enum plane plane) +{ + struct drm_crtc *crtc; + struct intel_framebuffer *intel_fb; + u32 val, base, size; + + crtc = intel_get_crtc_for_pipe(dev_priv->dev, pipe); + if (WARN(crtc->fb == NULL, + "no framebuffer attached to pipe %c\n", + pipe_name(pipe))) + return; + + intel_fb = to_intel_framebuffer(crtc->fb); + base = intel_fb->obj->gtt_offset; + size = intel_fb->obj->base.size; + + if (dev_priv->info->gen >= 4) + val = I915_READ(DSPSURF(plane)); + else + val = I915_READ(DSPADDR(plane)); + WARN(val < base || val >= base + size, + "mismatching framebuffer for plane %c attached to pipe %c, expected %x-%x found %x\n", + plane_name(plane), pipe_name(pipe), + base, base + size, val); +} + /** * intel_enable_plane - enable a display plane on a given pipe * @dev_priv: i915 private structure @@ -1290,6 +1318,7 @@ static void intel_enable_plane(struct drm_i915_private *dev_priv, /* If the pipe isn't enabled, we can't pump pixels and may hang */ assert_pipe_enabled(dev_priv, pipe); + assert_fb_bound_to_plane(dev_priv, pipe, plane); reg = DSPCNTR(plane); val = I915_READ(reg);