diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8848411..b77bd49 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3108,6 +3108,8 @@
 /* both Tx and Rx */
 #define  FDI_SCRAMBLING_ENABLE          (0<<7)
 #define  FDI_SCRAMBLING_DISABLE         (1<<7)
+/* Ivybridge */
+#define  FDI_AUTO_TRAIN_DONE		(1<<1)
 
 /* FDI_RX, FDI_X is hard-wired to Transcoder_X */
 #define _FDI_RXA_CTL             0xf000c
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 6455e0e..db46e4f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2292,7 +2292,76 @@ static void gen6_fdi_link_train(struct drm_crtc *crtc)
 	DRM_DEBUG_KMS("FDI train done.\n");
 }
 
-static void ironlake_fdi_enable(struct drm_crtc *crtc)
+/* On Ivybridge we can use auto training */
+static void ivb_fdi_link_train(struct drm_crtc *crtc)
+{
+	struct drm_device *dev = crtc->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	unsigned long start = jiffies_to_msecs(jiffies);
+	int pipe = intel_crtc->pipe;
+	u32 reg, temp, i, j;
+
+	/* Can't pair IVB & Ibex Peak */
+	BUG_ON(HAS_PCH_IBX(dev));
+
+	reg = FDI_TX_CTL(pipe);
+	temp = I915_READ(reg);
+	temp &= ~(7 << 19);
+	temp |= (intel_crtc->fdi_lanes - 1) << 19;
+	temp &= ~FDI_LINK_TRAIN_NONE;
+	I915_WRITE(reg, temp);
+
+	/* Enable auto training on TX and RX */
+	for (i = 0; i < ARRAY_SIZE(snb_b_fdi_train_param); i++) {
+		/* Try each vswing/pre-emphasis pair twice */
+		for (j = 0; j < 2; j++) {
+			reg = FDI_TX_CTL(pipe);
+			temp = I915_READ(reg);
+			temp |= FDI_AUTO_TRAINING;
+			temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
+			temp |= snb_b_fdi_train_param[i];
+			I915_WRITE(reg, temp | FDI_TX_ENABLE);
+
+			reg = FDI_RX_CTL(pipe);
+			temp = I915_READ(reg);
+			I915_WRITE(reg, temp | FDI_RX_ENABLE);
+			POSTING_READ(reg);
+
+			udelay(5);
+
+			reg = FDI_TX_CTL(pipe);
+			temp = I915_READ(reg);
+			if ((temp & FDI_AUTO_TRAIN_DONE) ||
+			    (I915_READ(reg) & FDI_AUTO_TRAIN_DONE)) {
+				DRM_DEBUG_KMS("FDI auto train complete in %d ms\n",
+					      jiffies_to_msecs(jiffies) - start);
+				goto done;
+			}
+
+			reg = FDI_TX_CTL(pipe);
+			temp = I915_READ(reg);
+			I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
+
+			reg = FDI_RX_CTL(pipe);
+			temp = I915_READ(reg);
+			I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
+			POSTING_READ(reg);
+			udelay(31); /* wait idle time before retrying */
+		}
+	}
+	DRM_ERROR("FDI auto train failed\n");
+	return;
+
+done:
+	reg = FDI_RX_CTL(pipe);
+	temp = I915_READ(reg);
+	temp |= FDI_FS_ERR_CORRECT_ENABLE | FDI_FE_ERR_CORRECT_ENABLE;
+	I915_WRITE(reg, temp);
+	POSTING_READ(reg);
+}
+
+static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
 {
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -2333,7 +2402,7 @@ static void ironlake_fdi_enable(struct drm_crtc *crtc)
 	}
 }
 
-static void ironlake_fdi_disable(struct drm_crtc *crtc)
+static void ironlake_fdi_pll_disable(struct drm_crtc *crtc)
 {
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -2555,9 +2624,9 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
 	is_pch_port = intel_crtc_driving_pch(crtc);
 
 	if (is_pch_port)
-		ironlake_fdi_enable(crtc);
+		ironlake_fdi_pll_enable(crtc);
 	else
-		ironlake_fdi_disable(crtc);
+		ironlake_fdi_pll_disable(crtc);
 
 	/* Enable panel fitting for LVDS */
 	if (dev_priv->pch_pf_size &&
@@ -2610,7 +2679,7 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
 	I915_WRITE(PF_CTL(pipe), 0);
 	I915_WRITE(PF_WIN_SZ(pipe), 0);
 
-	ironlake_fdi_disable(crtc);
+	ironlake_fdi_pll_disable(crtc);
 
 	/* This is a horrible layering violation; we should be doing this in
 	 * the connector/encoder ->prepare instead, but we don't always have
@@ -7297,6 +7366,8 @@ static void intel_init_display(struct drm_device *dev)
 				dev_priv->display.update_wm = NULL;
 			}
 			dev_priv->display.train_fdi = gen6_fdi_link_train;
+		} else if (IS_IVYBRIDGE(dev)) {
+			dev_priv->display.train_fdi = ivb_fdi_link_train;
 		} else
 			dev_priv->display.update_wm = NULL;
 	} else if (IS_PINEVIEW(dev)) {
