From patchwork Fri May 6 21:04:37 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eric Anholt X-Patchwork-Id: 763302 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by demeter2.kernel.org (8.14.4/8.14.3) with ESMTP id p46M7Exk015361 for ; Fri, 6 May 2011 22:07:39 GMT Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 696A89ECC4 for ; Fri, 6 May 2011 15:07:13 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from annarchy.freedesktop.org (annarchy.freedesktop.org [131.252.210.176]) by gabe.freedesktop.org (Postfix) with ESMTP id 751A99E7B6; Fri, 6 May 2011 15:06:53 -0700 (PDT) Received: from pollan.anholt.net (annarchy.freedesktop.org [127.0.0.1]) by annarchy.freedesktop.org (Postfix) with ESMTP id 2DD8413004E; Fri, 6 May 2011 15:06:52 -0700 (PDT) Received: by pollan.anholt.net (Postfix, from userid 1000) id 053A032C06C; Fri, 6 May 2011 14:04:39 -0700 (PDT) From: Eric Anholt To: intel-gfx@lists.freedesktop.org Date: Fri, 6 May 2011 14:04:37 -0700 Message-Id: <1304715877-27032-1-git-send-email-eric@anholt.net> X-Mailer: git-send-email 1.7.4.4 Subject: [Intel-gfx] [PATCH] Add Ivybridge support to intel_gpu_dump and the BLT tests. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.11 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter2.kernel.org [140.211.167.43]); Fri, 06 May 2011 22:07:39 +0000 (UTC) --- lib/intel_batchbuffer.c | 2 +- lib/intel_chipset.h | 29 +++++++++++++++++++++++++---- tests/gem_exec_blt.c | 2 +- tests/gem_linear_blits.c | 2 +- tools/intel_gpu_dump.c | 2 +- 5 files changed, 29 insertions(+), 8 deletions(-) diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c index a2f9ae7..111f65d 100644 --- a/lib/intel_batchbuffer.c +++ b/lib/intel_batchbuffer.c @@ -108,7 +108,7 @@ intel_batchbuffer_flush(struct intel_batchbuffer *batch) batch->ptr = NULL; ring = 0; - if (IS_GEN6(batch->devid)) + if (HAS_BLT_RING(batch->devid)) ring = I915_EXEC_BLT; ret = drm_intel_bo_mrb_exec(batch->bo, used, NULL, 0, 0, ring); assert(ret == 0); diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h index d1e5088..bf6815f 100755 --- a/lib/intel_chipset.h +++ b/lib/intel_chipset.h @@ -78,13 +78,21 @@ #define PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS 0x0126 #define PCI_CHIP_SANDYBRIDGE_S 0x010A /* server */ +#define PCI_CHIP_IVYBRIDGE_M_GT1 0x0156 +#define PCI_CHIP_IVYBRIDGE_M_GT2 0x0166 +#define PCI_CHIP_IVYBRIDGE_D_GT1 0x0152 +#define PCI_CHIP_IVYBRIDGE_D_GT1_SERVER 0x015a +#define PCI_CHIP_IVYBRIDGE_D_GT2 0x0162 + #define IS_MOBILE(devid) (devid == PCI_CHIP_I855_GM || \ devid == PCI_CHIP_I915_GM || \ devid == PCI_CHIP_I945_GM || \ devid == PCI_CHIP_I945_GME || \ devid == PCI_CHIP_I965_GM || \ devid == PCI_CHIP_I965_GME || \ - devid == PCI_CHIP_GM45_GM || IS_IGD(devid)) + devid == PCI_CHIP_GM45_GM || IS_IGD(devid) || \ + devid == PCI_CHIP_IVYBRIDGE_M_GT1 || \ + devid == PCI_CHIP_IVYBRIDGE_M_GT2) #define IS_G45(devid) (devid == PCI_CHIP_IGD_E_G || \ devid == PCI_CHIP_Q45_G || \ @@ -135,15 +143,28 @@ devid == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS || \ devid == PCI_CHIP_SANDYBRIDGE_S) +#define IS_GEN7(devid) (devid == PCI_CHIP_IVYBRIDGE_M_GT1 || \ + devid == PCI_CHIP_IVYBRIDGE_M_GT2 || \ + devid == PCI_CHIP_IVYBRIDGE_D_GT1 || \ + devid == PCI_CHIP_IVYBRIDGE_D_GT1_SERVER || \ + devid == PCI_CHIP_IVYBRIDGE_D_GT2) + + #define IS_965(devid) (IS_GEN4(devid) || \ IS_GEN5(devid) || \ - IS_GEN6(devid)) + IS_GEN6(devid) || \ + IS_GEN7(devid)) #define IS_INTEL(devid) (IS_GEN2(devid) || \ IS_GEN3(devid) || \ IS_GEN4(devid) || \ IS_GEN5(devid) || \ - IS_GEN6(devid)) + IS_GEN6(devid) || \ + IS_GEN7(devid)) #define HAS_PCH_SPLIT(devid) (IS_GEN5(devid) || \ - IS_GEN6(devid)) + IS_GEN6(devid) || \ + IS_GEN7(devid)) + +#define HAS_BLT_RING(devid) (IS_GEN6(devid) || \ + IS_GEN7(devid)) diff --git a/tests/gem_exec_blt.c b/tests/gem_exec_blt.c index 9ea4c4e..19eb716 100644 --- a/tests/gem_exec_blt.c +++ b/tests/gem_exec_blt.c @@ -253,7 +253,7 @@ static void run(int object_size) exec[2].rsvd2 = 0; ring = 0; - if (IS_GEN6(intel_get_drm_devid(fd))) + if (HAS_BLT_RING(intel_get_drm_devid(fd))) ring = I915_EXEC_BLT; execbuf.buffers_ptr = (uintptr_t)exec; diff --git a/tests/gem_linear_blits.c b/tests/gem_linear_blits.c index b408f8d..ae188ff 100644 --- a/tests/gem_linear_blits.c +++ b/tests/gem_linear_blits.c @@ -189,7 +189,7 @@ copy(int fd, uint32_t dst, uint32_t src) exec.DR1 = exec.DR4 = 0; exec.num_cliprects = 0; exec.cliprects_ptr = 0; - exec.flags = IS_GEN6(intel_get_drm_devid(fd)) ? I915_EXEC_BLT : 0; + exec.flags = HAS_BLT_RING(intel_get_drm_devid(fd)) ? I915_EXEC_BLT : 0; exec.rsvd1 = exec.rsvd2 = 0; ret = drmIoctl(fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &exec); diff --git a/tools/intel_gpu_dump.c b/tools/intel_gpu_dump.c index 0049f64..74acd3d 100644 --- a/tools/intel_gpu_dump.c +++ b/tools/intel_gpu_dump.c @@ -328,7 +328,7 @@ main (int argc, char *argv[]) printf("ESR: 0x%08x\n", INREG(ESR)); printf("PGTBL_ER: 0x%08x\n", INREG(PGTBL_ER)); - if (IS_GEN6(devid)) { + if (IS_GEN6(devid) || IS_GEN7(devid)) { instdone = INREG(GEN6_INSTDONE_1); instdone1 = INREG(GEN6_INSTDONE_2);