@@ -81,12 +81,3 @@
#define PCI_CHIP_IVYBRIDGE_M_GT1 0x0156 /* Mobile */
#define PCI_CHIP_IVYBRIDGE_M_GT2 0x0166
#define PCI_CHIP_IVYBRIDGE_S_GT1 0x015a /* Server */
-
-#define IS_G45(devid) (devid == PCI_CHIP_IGD_E_G || \
- devid == PCI_CHIP_Q45_G || \
- devid == PCI_CHIP_G45_G || \
- devid == PCI_CHIP_G41_G || \
- devid == PCI_CHIP_B43_G || \
- devid == PCI_CHIP_B43_G1)
-#define IS_GM45(devid) (devid == PCI_CHIP_GM45_GM)
-#define IS_G4X(devid) (IS_G45(devid) || IS_GM45(devid))
@@ -726,7 +726,7 @@ intelInitContext(struct intel_context *intel,
intel->needs_ff_sync = GL_TRUE;
intel->has_luminance_srgb = GL_TRUE;
} else if (intel->intelScreen->chipset.gen == 4) {
- if (IS_G4X(intel->intelScreen->deviceID)) {
+ if (intel->intelScreen->chipset.is_g4x) {
intel->has_luminance_srgb = GL_TRUE;
intel->is_g4x = GL_TRUE;
}
@@ -479,6 +479,7 @@ static const struct intel_chipset intel_chipset_i965 = {
static const struct intel_chipset intel_chipset_g4x = {
.gen = 4,
+ .is_g4x = GL_TRUE,
.urb_size = 384,
.vs_max_threads = 32,
.wm_max_threads = 10 * 5
@@ -36,7 +36,7 @@
struct intel_chipset {
int gen;
- GLboolean is_945;
+ GLboolean is_945, is_g4x;
/* WM maximum threads is number of EUs times number of threads per EU. */
int wm_max_threads;