From patchwork Fri Jul 1 23:35:07 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jesse Barnes X-Patchwork-Id: 939602 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by demeter2.kernel.org (8.14.4/8.14.4) with ESMTP id p61NjvCj012339 for ; Fri, 1 Jul 2011 23:46:18 GMT Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 946019E8C4 for ; Fri, 1 Jul 2011 16:35:33 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from oproxy3-pub.bluehost.com (oproxy3-pub.bluehost.com [69.89.21.8]) by gabe.freedesktop.org (Postfix) with SMTP id 2D4519E79E for ; Fri, 1 Jul 2011 16:35:15 -0700 (PDT) Received: (qmail 18231 invoked by uid 0); 1 Jul 2011 23:35:14 -0000 Received: from unknown (HELO box514.bluehost.com) (74.220.219.114) by oproxy3.bluehost.com with SMTP; 1 Jul 2011 23:35:14 -0000 DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=default; d=virtuousgeek.org; h=Received:From:To:Cc:Subject:Date:Message-Id:X-Mailer:X-Identified-User; b=dHymcCwb3ByJ+RTsTVIzr5MKvhQnbTfB+xkQF7ATTLPo600I3Cc054CCbe1qQ/1r60ItxwnmMOjyCMQ3kHOXBQGDkJYoyB3yz4RceW0RC+FdG+tBe0tlXCG/JOo/b8zT; Received: from c-67-161-37-189.hsd1.ca.comcast.net ([67.161.37.189] helo=localhost.localdomain) by box514.bluehost.com with esmtpsa (TLSv1:AES256-SHA:256) (Exim 4.69) (envelope-from ) id 1QcnEw-0008Jl-6W; Fri, 01 Jul 2011 17:35:14 -0600 From: Jesse Barnes To: intel-gfx@lists.freedesktop.org Date: Fri, 1 Jul 2011 16:35:07 -0700 Message-Id: <1309563307-5480-1-git-send-email-jbarnes@virtuousgeek.org> X-Mailer: git-send-email 1.7.4.1 X-Identified-User: {10642:box514.bluehost.com:virtuous:virtuousgeek.org} {sentby:smtp auth 67.161.37.189 authed with jbarnes@virtuousgeek.org} Subject: [Intel-gfx] [PATCH] drm/i915: set cache sharing policy to max sharing on SNB+ X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.11 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter2.kernel.org [140.211.167.43]); Fri, 01 Jul 2011 23:46:18 +0000 (UTC) By default, the GPU will only share a very small portion of the CPU cache. With this change, both the GPU and CPU will have full access to the cache, which should help (sometimes a lot) in most cases. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/i915_reg.h | 5 +++++ drivers/gpu/drm/i915/intel_display.c | 7 +++++++ 2 files changed, 12 insertions(+), 0 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 4a446b1..eac59f1 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -78,6 +78,11 @@ #define GRDOM_RENDER (1<<2) #define GRDOM_MEDIA (3<<2) +#define GEN6_MBCUNIT_CFG 0x900c /* for LLC config */ +#define GEN6_MBC_LLC_CFG_MASK (3<<21) +#define GEN6_MBC_LLC_CFG_FULL (1<<21) /* full sharing of 16/16ths of the cache */ +#define GEN6_MBC_LLC_CFG_MIN (3<<21) /* only 1/16th of the cache is shared */ + #define GEN6_GDRST 0x941c #define GEN6_GRDOM_FULL (1 << 0) #define GEN6_GRDOM_RENDER (1 << 1) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 823b8d9..0ed4ed2 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -7279,6 +7279,7 @@ void gen6_update_ring_freq(struct drm_i915_private *dev_priv) int min_freq = 15; int gpu_freq, ia_freq, max_ia_freq; int scaling_factor = 180; + u32 mbccfg; max_ia_freq = cpufreq_quick_get_max(0); /* @@ -7293,6 +7294,12 @@ void gen6_update_ring_freq(struct drm_i915_private *dev_priv) mutex_lock(&dev_priv->dev->struct_mutex); + /* Update the cache sharing policy here as well */ + mbccfg = I915_READ(GEN6_MBCUNIT_CFG); + mbccfg &= ~GEN6_MBC_LLC_CFG_MASK; + mbccfg |= GEN6_MBC_LLC_CFG_FULL; + I915_WRITE(GEN6_MBCUNIT_CFG, mbccfg); + /* * For each potential GPU frequency, load a ring frequency we'd like * to use for memory access. We do this by specifying the IA frequency