From patchwork Thu Jul 14 21:21:15 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kenneth Graunke X-Patchwork-Id: 975862 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by demeter1.kernel.org (8.14.4/8.14.4) with ESMTP id p6ELPh3x019478 for ; Thu, 14 Jul 2011 21:26:04 GMT Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 653A09E9EA for ; Thu, 14 Jul 2011 14:25:43 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from homiemail-a6.g.dreamhost.com (caiajhbdccac.dreamhost.com [208.97.132.202]) by gabe.freedesktop.org (Postfix) with ESMTP id B45789F308 for ; Thu, 14 Jul 2011 14:24:09 -0700 (PDT) Received: from homiemail-a6.g.dreamhost.com (localhost [127.0.0.1]) by homiemail-a6.g.dreamhost.com (Postfix) with ESMTP id 4E983598076; Thu, 14 Jul 2011 14:24:09 -0700 (PDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=whitecape.org; h=from:to:cc :subject:date:message-id:in-reply-to:references; q=dns; s= whitecape.org; b=nJeLk+Cw8BY0py0orVpB8ikb2UAPPX6VosYhnPJZVZwKgHx attFl+f52/tB0ciwUddO3blcU2+SViFbImV7feFnPiKkOlJAiawOLbgCxRj2Sfd7 ZCuqgCXlVi0cUIZQTc7v9LgKD9r3XlNIUVGTVBsDhuMUsYLz26IY7BBKqAWc= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=whitecape.org; h=from:to :cc:subject:date:message-id:in-reply-to:references; s= whitecape.org; bh=I/kCzy49LQ0GRx6+hzYxDnm8/wY=; b=mPaqf44GTPOxZw MFT257npBNlkzmEUIDhMNzcicGvX5asUfklAPu6pK5iBC2blQsn0WFl7prP1RTf/ +J7ctKcqKoPG2s0njtmTie28GLPKRHN8N7bqcqJBWRNKZPIT7mNhbNINVcFmunHs IylYgIGefx0Y5ucvfKbdc5v230ReY= Received: from localhost (fruit.freedesktop.org [131.252.210.190]) (using TLSv1 with cipher DHE-RSA-AES128-SHA (128/128 bits)) (No client certificate requested) (Authenticated sender: kenneth@whitecape.org) by homiemail-a6.g.dreamhost.com (Postfix) with ESMTPSA id E123859806C; Thu, 14 Jul 2011 14:24:08 -0700 (PDT) From: Kenneth Graunke To: intel-gfx@lists.freedesktop.org Date: Thu, 14 Jul 2011 14:21:15 -0700 Message-Id: <1310678483-7494-3-git-send-email-kenneth@whitecape.org> X-Mailer: git-send-email 1.7.4.4 In-Reply-To: <1310678483-7494-1-git-send-email-kenneth@whitecape.org> References: <1310678483-7494-1-git-send-email-kenneth@whitecape.org> Subject: [Intel-gfx] [PATCH 02/10] render: Update SURFACE_STATE for Ivybridge. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.11 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Thu, 14 Jul 2011 21:26:05 +0000 (UTC) Signed-off-by: Kenneth Graunke --- src/i965_render.c | 91 +++++++++++++++++++++++++++++++++++++++++++++++----- 1 files changed, 82 insertions(+), 9 deletions(-) diff --git a/src/i965_render.c b/src/i965_render.c index 5ab53c4..bb3c2b7 100644 --- a/src/i965_render.c +++ b/src/i965_render.c @@ -723,10 +723,10 @@ typedef struct _brw_cc_unit_state_padded { char pad[64 - sizeof(struct brw_cc_unit_state)]; } brw_cc_unit_state_padded; -typedef struct brw_surface_state_padded { - struct brw_surface_state state; - char pad[32 - sizeof(struct brw_surface_state)]; -} brw_surface_state_padded; +#ifndef MAX +#define MAX(a, b) ((a) > (b) ? (a) : (b)) +#endif +#define SURFACE_STATE_PADDED_SIZE ALIGN(MAX(sizeof(struct brw_surface_state), sizeof(struct gen7_surface_state)), 32) struct gen4_cc_unit_state { /* Index by [src_blend][dst_blend] */ @@ -1161,7 +1161,7 @@ static sampler_state_extend_t sampler_state_extend_from_picture(int repeat_type) * picture in the given surface state buffer. */ static int -i965_set_picture_surface_state(intel_screen_private *intel, +gen4_set_picture_surface_state(intel_screen_private *intel, PicturePtr picture, PixmapPtr pixmap, Bool is_dst) { @@ -1215,7 +1215,70 @@ i965_set_picture_surface_state(intel_screen_private *intel, priv->bo); offset = intel->surface_used; - intel->surface_used += sizeof(struct brw_surface_state_padded); + intel->surface_used += SURFACE_STATE_PADDED_SIZE; + + if (is_dst) + priv->dst_bound = offset; + else + priv->src_bound = offset; + + return offset; +} + +static int +gen7_set_picture_surface_state(intel_screen_private *intel, + PicturePtr picture, PixmapPtr pixmap, + Bool is_dst) +{ + struct intel_pixmap *priv = intel_get_pixmap_private(pixmap); + struct gen7_surface_state *ss; + uint32_t write_domain, read_domains; + int offset; + + if (is_dst) { + write_domain = I915_GEM_DOMAIN_RENDER; + read_domains = I915_GEM_DOMAIN_RENDER; + } else { + write_domain = 0; + read_domains = I915_GEM_DOMAIN_SAMPLER; + } + intel_batch_mark_pixmap_domains(intel, priv, + read_domains, write_domain); + if (is_dst) { + if (priv->dst_bound) + return priv->dst_bound; + } else { + if (priv->src_bound) + return priv->src_bound; + } + + ss = (struct gen7_surface_state *) + (intel->surface_data + intel->surface_used); + + memset(ss, 0, sizeof(*ss)); + ss->ss0.surface_type = BRW_SURFACE_2D; + if (is_dst) + ss->ss0.surface_format = i965_get_dest_format(picture); + else + ss->ss0.surface_format = i965_get_card_format(picture); + + ss->ss0.tile_walk = 0; /* Tiled X */ + ss->ss0.tiled_surface = intel_pixmap_tiled(pixmap) ? 1 : 0; + ss->ss1.base_addr = priv->bo->offset; + + ss->ss2.height = pixmap->drawable.height - 1; + ss->ss2.width = pixmap->drawable.width - 1; + ss->ss3.pitch = intel_pixmap_pitch(pixmap) - 1; + + dri_bo_emit_reloc(intel->surface_bo, + read_domains, write_domain, + 0, + intel->surface_used + + offsetof(struct gen7_surface_state, ss1), + priv->bo); + + offset = intel->surface_used; + intel->surface_used += SURFACE_STATE_PADDED_SIZE; if (is_dst) priv->dst_bound = offset; @@ -1225,6 +1288,16 @@ i965_set_picture_surface_state(intel_screen_private *intel, return offset; } +static inline int +i965_set_picture_surface_state(intel_screen_private *intel, + PicturePtr picture, PixmapPtr pixmap, + Bool is_dst) +{ + if (INTEL_INFO(intel)->gen < 70) + return gen4_set_picture_surface_state(intel, picture, pixmap, is_dst); + return gen7_set_picture_surface_state(intel, picture, pixmap, is_dst); +} + static void gen4_composite_vertex_elements(struct intel_screen_private *intel) { struct gen4_render_state *render_state = intel->gen4_render_state; @@ -1968,7 +2041,7 @@ i965_prepare_composite(int op, PicturePtr source_picture, } if (sizeof(intel->surface_data) - intel->surface_used < - 4 * sizeof(struct brw_surface_state_padded)) + 4 * SURFACE_STATE_PADDED_SIZE) i965_surface_flush(intel); intel->needs_render_state_emit = TRUE; @@ -2014,11 +2087,11 @@ static void i965_bind_surfaces(struct intel_screen_private *intel) { uint32_t *binding_table; - assert(intel->surface_used + 4 * sizeof(struct brw_surface_state_padded) <= sizeof(intel->surface_data)); + assert(intel->surface_used + 4 * SURFACE_STATE_PADDED_SIZE <= sizeof(intel->surface_data)); binding_table = (uint32_t*) (intel->surface_data + intel->surface_used); intel->surface_table = intel->surface_used; - intel->surface_used += sizeof(struct brw_surface_state_padded); + intel->surface_used += SURFACE_STATE_PADDED_SIZE; binding_table[0] = i965_set_picture_surface_state(intel,