From patchwork Sun Sep 4 15:35:00 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 1124122 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by demeter2.kernel.org (8.14.4/8.14.4) with ESMTP id p84Ga0vu020468 for ; Sun, 4 Sep 2011 16:36:20 GMT Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B048FA1B29 for ; Sun, 4 Sep 2011 09:36:00 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-ey0-f169.google.com (mail-ey0-f169.google.com [209.85.215.169]) by gabe.freedesktop.org (Postfix) with ESMTP id DEB3BA1AF9 for ; Sun, 4 Sep 2011 09:34:49 -0700 (PDT) Received: by eye22 with SMTP id 22so3646755eye.0 for ; Sun, 04 Sep 2011 09:34:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=Bl8CeT4i+fhDHGcX+daKN0FLcn0EaBQbcf+OmsYbo1I=; b=aBR0iolz2a0Nrz7oF6i8s5DSP+sOVBZMGmLCMxVpFv2f43b3O4FxnGYxw3BrKmXAkv NsUruwuNJkHwsJcg4k+IzoqqeR5Eau+iCexFnvAqd5Ot3X4Zh0Sv3rtrsL4RkB23XI0i P53bcSZfntfkOI65OWvzUO7xH5IyUe3nhWvPg= Received: by 10.14.15.223 with SMTP id f71mr861428eef.53.1315154088668; Sun, 04 Sep 2011 09:34:48 -0700 (PDT) Received: from localhost.localdomain (178-83-130-250.dynamic.hispeed.ch [178.83.130.250]) by mx.google.com with ESMTPS id q50sm6207272eef.9.2011.09.04.09.34.47 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 04 Sep 2011 09:34:48 -0700 (PDT) From: Daniel Vetter To: intel-gfx@lists.freedesktop.org Date: Sun, 4 Sep 2011 17:35:00 +0200 Message-Id: <1315150502-12537-2-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.7.6 In-Reply-To: <1315150502-12537-1-git-send-email-daniel.vetter@ffwll.ch> References: <20110904084953.16cd10a2@bwidawsk.net> <1315150502-12537-1-git-send-email-daniel.vetter@ffwll.ch> Cc: Daniel Vetter , Ben Widawsky Subject: [Intel-gfx] [PATCH 1/3] drm/i915: close PM interrupt masking races in the irq handler X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.11 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter2.kernel.org [140.211.167.43]); Sun, 04 Sep 2011 16:36:20 +0000 (UTC) Quoting Chris Wilson's more concise description: "Ah I think I see the problem. As you point out we only mask the current interrupt received, so that if we have a task pending (and so IMR != 0) we actually unmask the pending interrupt and so could receive it again before the tasklet is finally kicked off by the grumpy scheduler." So we need the hw to issue PM interrupts A, B, A while the scheduler is hating us and refuses to run the rps work item. On receiving PM interrupt A we hit the WARN because dev_priv->pm_iir == PM_A | PM_B Also add a posting read as suggested by Chris to ensure proper ordering of the writes to PMIMR and PMIIR. Just in case somebody weakens write ordering. Signed-off-by: Daniel Vetter Reviewed-by: Ben Widawsky --- drivers/gpu/drm/i915/i915_irq.c | 6 ++++-- 1 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 9cbb0cd..2fdd9f9 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -536,8 +536,9 @@ static irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS) unsigned long flags; spin_lock_irqsave(&dev_priv->rps_lock, flags); WARN(dev_priv->pm_iir & pm_iir, "Missed a PM interrupt\n"); - I915_WRITE(GEN6_PMIMR, pm_iir); dev_priv->pm_iir |= pm_iir; + I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir); + POSTING_READ(GEN6_PMIMR); spin_unlock_irqrestore(&dev_priv->rps_lock, flags); queue_work(dev_priv->wq, &dev_priv->rps_work); } @@ -649,8 +650,9 @@ static irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS) unsigned long flags; spin_lock_irqsave(&dev_priv->rps_lock, flags); WARN(dev_priv->pm_iir & pm_iir, "Missed a PM interrupt\n"); - I915_WRITE(GEN6_PMIMR, pm_iir); dev_priv->pm_iir |= pm_iir; + I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir); + POSTING_READ(GEN6_PMIMR); spin_unlock_irqrestore(&dev_priv->rps_lock, flags); queue_work(dev_priv->wq, &dev_priv->rps_work); }