From patchwork Thu Sep 8 12:00:21 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 1129602 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by demeter1.kernel.org (8.14.4/8.14.4) with ESMTP id p88D1698029482 for ; Thu, 8 Sep 2011 13:01:30 GMT Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 30C4C6B2EA for ; Thu, 8 Sep 2011 06:01:06 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wy0-f177.google.com (mail-wy0-f177.google.com [74.125.82.177]) by gabe.freedesktop.org (Postfix) with ESMTP id 6D88EA196C for ; Thu, 8 Sep 2011 06:00:17 -0700 (PDT) Received: by wyh11 with SMTP id 11so668235wyh.36 for ; Thu, 08 Sep 2011 06:00:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=G8IXGMjP5o1/jr6BSZaUrLT2F41tq3bgunAssTzTZJ8=; b=Ud8XSB5rL4/NnPOuXAIXx9BGI77EpIq7g4ErebJL3m/ejXIDfWmBWPlpLVqmZRYvbH iLbDmpQrJJUrfsfSxhblikqobf/1dQ8DFSxxd5EG+iP66Cpm2mO6c1Q5XSWenc1WLDIy rUtETRI8VfJVxjqsJ6Srm5zvegArBglcOtU2k= Received: by 10.216.169.203 with SMTP id n53mr696423wel.70.1315486816009; Thu, 08 Sep 2011 06:00:16 -0700 (PDT) Received: from localhost.localdomain (178-83-130-250.dynamic.hispeed.ch [178.83.130.250]) by mx.google.com with ESMTPS id ev5sm4161718wbb.11.2011.09.08.06.00.14 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 08 Sep 2011 06:00:15 -0700 (PDT) From: Daniel Vetter To: intel-gfx@lists.freedesktop.org Date: Thu, 8 Sep 2011 14:00:21 +0200 Message-Id: <1315483222-2195-2-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.7.6 In-Reply-To: <1315483222-2195-1-git-send-email-daniel.vetter@ffwll.ch> References: <1315483222-2195-1-git-send-email-daniel.vetter@ffwll.ch> Cc: Daniel Vetter , Ben Widawsky Subject: [Intel-gfx] [PATCH 2/3] drm/i915: close PM interrupt masking races in the rps work func X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.11 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Thu, 08 Sep 2011 13:02:18 +0000 (UTC) This patch closes the following race: We get a PM interrupt A, mask it, set dev_priv->iir = PM_A and kick of the work item. Scheduler isn't grumpy, so the work queue takes rps_lock, grabs pm_iir = dev_priv->pm_iir and pm_imr = READ(PMIMR). Note that pm_imr == pm_iir because we've just masked the interrupt we've got. Now hw sends out PM interrupt B (not masked), we process it and mask it. Later on the irq handler also clears PMIIR. Then the work item proceeds and at the end clears PMIMR. Because (local) pm_imr == pm_iir we have pm_imr & ~pm_iir == 0 so all interrupts are enabled. Hardware is still interrupt-happy, and sends out a new PM interrupt B. PMIMR doesn't mask B (it does not mask anything), PMIIR is cleared, so we get it and hit the WARN in the interrupt handler (because dev_priv->pm_iir == PM_B). That's why I've moved the WRITE(PMIMR, 0) up under the protection of the rps_lock. And write an uncoditional 0 to PMIMR, because that's what we'll do anyway. This races looks much more likely because we can arbitrarily extend the window by grabing dev->struct mutex right after the irq handler has processed the first PM_B interrupt. Signed-off-by: Daniel Vetter Cc: Ben Widawsky Reviewed-by: Ben Widawsky --- drivers/gpu/drm/i915/i915_irq.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 2fdd9f9..21ebcbd 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -383,6 +383,7 @@ static void gen6_pm_rps_work(struct work_struct *work) pm_iir = dev_priv->pm_iir; dev_priv->pm_iir = 0; pm_imr = I915_READ(GEN6_PMIMR); + I915_WRITE(GEN6_PMIMR, 0); spin_unlock_irq(&dev_priv->rps_lock); if (!pm_iir) @@ -420,7 +421,6 @@ static void gen6_pm_rps_work(struct work_struct *work) * an *extremely* unlikely race with gen6_rps_enable() that is prevented * by holding struct_mutex for the duration of the write. */ - I915_WRITE(GEN6_PMIMR, pm_imr & ~pm_iir); mutex_unlock(&dev_priv->dev->struct_mutex); }