From patchwork Tue Jul 3 09:28:27 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 1150451 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id 33C843FE4F for ; Tue, 3 Jul 2012 11:02:15 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0E62F9F7CD for ; Tue, 3 Jul 2012 04:02:15 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-we0-f177.google.com (mail-we0-f177.google.com [74.125.82.177]) by gabe.freedesktop.org (Postfix) with ESMTP id 5F01C9F752 for ; Tue, 3 Jul 2012 03:35:12 -0700 (PDT) Received: by mail-we0-f177.google.com with SMTP id b13so1638092wer.36 for ; Tue, 03 Jul 2012 03:35:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=LV7lzX7d3eRf1SyUfGYKjeW6rG0XEICQQCqnAralONQ=; b=YSn4SQmknMbK/7IxNNtqNh6/fUgpWMJQNgr2Fowh0oMGeyjIMqlk9QQPuvwVzz+Jpx ir3GtZzFFvIwOgBVsJgGyhScEhcPu+X7ZJemFRlXbLJnQodOZDOX8qJF8InIUjPMZifT Butp184URx8DYKaalZQwHvmV+Hwf22CDp3ie4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=LV7lzX7d3eRf1SyUfGYKjeW6rG0XEICQQCqnAralONQ=; b=RekAIqHYVmncWMaql4v4eVDBPpnGvmfjrjMvWscBuQssyagyXZ8aafU29jLoYhHFX+ TeBp5u0jajyivUoUUUAO4NzSbyE5Ovt8nubQi7x6B4zZAzTzC94TIFvvfZcJs6C+q63Q X5Q51CG7fBI1FGBCQsMwbbRiErEcCFczac695s+nXE6V1qxyq0Bqkl/vPCgYq/HzeGRT /5kDKxorMqW3z24N23x8yefo8HDoP8f3kgkfRzQhr7TQpQ6lu3COZPumQzO2nbfoxvLd wLzd0ZscocilG085nRZ7ABc4AyaUK4qL4JB47K/W/UDujugUFlXgueGkhqA5+Z2Jxt18 WW4g== Received: by 10.216.0.212 with SMTP id 62mr3803713web.92.1341311711973; Tue, 03 Jul 2012 03:35:11 -0700 (PDT) Received: from wespe.ffwll.local (178-83-130-250.dynamic.hispeed.ch. [178.83.130.250]) by mx.google.com with ESMTPS id e9sm14845138wiw.10.2012.07.03.03.35.10 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 03 Jul 2012 03:35:11 -0700 (PDT) From: Daniel Vetter To: Intel Graphics Development Date: Tue, 3 Jul 2012 11:28:27 +0200 Message-Id: <1341307715-3886-36-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.7.7.6 In-Reply-To: <1341307715-3886-1-git-send-email-daniel.vetter@ffwll.ch> References: <1341307715-3886-1-git-send-email-daniel.vetter@ffwll.ch> X-Gm-Message-State: ALoCoQklsY2oQNXzlCwkDNZJ7gz4wqX2+WFDM2/Q1+8XKs4EA4toPCW/tAV/Aso/d8P8sd8TSjNP Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH 35/43] drm/i915/dp: implement get_hw_state X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Also add some macros to make the pipe computation a bit easier. Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_reg.h | 2 + drivers/gpu/drm/i915/intel_dp.c | 50 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 52 insertions(+), 0 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 3b9c65e..428c3f3 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4008,6 +4008,8 @@ #define PORT_TRANS_C_SEL_CPT (2<<29) #define PORT_TRANS_SEL_MASK (3<<29) #define PORT_TRANS_SEL_CPT(pipe) ((pipe) << 29) +#define PORT_TO_PIPE_CPT(val) (((val) & (1<<30)) >> 30) +#define PORT_TO_PIPE(val) (((val) & PORT_TRANS_SEL_MASK) >> 29) #define TRANS_DP_CTL_A 0xe0300 #define TRANS_DP_CTL_B 0xe1300 diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 5b4498f..648c6e5 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -1277,6 +1277,54 @@ static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) } } +static bool intel_dp_get_hw_state(struct intel_encoder *encoder, + enum pipe *pipe) +{ + struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); + struct drm_device *dev = encoder->base.dev; + struct drm_i915_private *dev_priv = dev->dev_private; + u32 tmp = I915_READ(intel_dp->output_reg); + + if (!(tmp & DP_PORT_EN)) + return false; + + if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) { + *pipe = PORT_TO_PIPE_CPT(tmp); + } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) { + *pipe = PORT_TO_PIPE(tmp); + } else { + u32 trans_sel; + u32 trans_dp; + int i; + + switch (intel_dp->output_reg) { + case PCH_DP_B: + trans_sel = TRANS_DP_PORT_SEL_B; + break; + case PCH_DP_C: + trans_sel = TRANS_DP_PORT_SEL_C; + break; + case PCH_DP_D: + trans_sel = TRANS_DP_PORT_SEL_D; + break; + default: + return true; + } + + for_each_pipe(i) { + trans_dp = I915_READ(TRANS_DP_CTL(i)); + if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) { + *pipe = i; + return true; + } + } + } + + DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", intel_dp->output_reg); + + return true; +} + static void intel_disable_dp(struct intel_encoder *encoder) { struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); @@ -2496,6 +2544,8 @@ intel_dp_init(struct drm_device *dev, int output_reg) intel_encoder->enable = intel_enable_dp; intel_encoder->disable = intel_disable_dp; + intel_encoder->get_hw_state = intel_dp_get_hw_state; + intel_connector->get_hw_state = intel_connector_get_hw_state; /* Set up the DDC bus. */ switch (output_reg) {