From patchwork Thu Jul 5 10:17:30 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 1159071 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id 439D53FD4F for ; Thu, 5 Jul 2012 10:18:39 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4936BA0DEE for ; Thu, 5 Jul 2012 03:18:39 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wi0-f171.google.com (mail-wi0-f171.google.com [209.85.212.171]) by gabe.freedesktop.org (Postfix) with ESMTP id 380B09EEAB for ; Thu, 5 Jul 2012 03:17:39 -0700 (PDT) Received: by wibhq4 with SMTP id hq4so4507271wib.12 for ; Thu, 05 Jul 2012 03:17:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=CVfVYoVQs1x9eo8NvT//kK2VupvH3VCsHWxsg5Dxq9s=; b=JKCDuc5WCj+85VCoDtiSRO3m0txidNDB5buHeSGruLLMMmJ2ewls06Zf3foglP2J12 nN+RsdcRjut5oyXB0TUuCADQf3SXcelQYBqoQLZw8qUX7+utGVF6H22Kb84U+E1M/mMJ uLDrCd5kv5EdCLkV0FWgCEjm/5Q/bfl+UkusM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=CVfVYoVQs1x9eo8NvT//kK2VupvH3VCsHWxsg5Dxq9s=; b=Qj5rHO/Ev+muTi+wEnwbxG+30Sy1ECiZHTxB83vjsCBV0vnyEl7c5bi7VqPpyMLjNZ k/eYOpjLowZ7nqFC8dfql/9JzsqBE9LAekhtOccs0dCuub5/YWJooeBVP8JfvmM5f0/T 1EW9Mi44Z4t2SnGkfuyo5xAS/ZRuizO1suKcJ2hNaGikGJuj9FCtgMvmKZSgPtfrQdJf 22sT3+0c5Kl1YRlx8WAuP9M1BuGZqXpGNZkQvWaweBhKKP340kxi1pgoi6mL1Z3looX6 FaSQd8HC0JpaHHw2SFGPSHAk/9FCS2GwJODuGNyL1E52Ih0fOhsg3X+z/548xk5OCjO/ oZ5Q== Received: by 10.216.218.220 with SMTP id k70mr3602369wep.165.1341483458264; Thu, 05 Jul 2012 03:17:38 -0700 (PDT) Received: from bremse.ffwll.local (178-83-130-250.dynamic.hispeed.ch. [178.83.130.250]) by mx.google.com with ESMTPS id q6sm42732897wiy.0.2012.07.05.03.17.36 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 05 Jul 2012 03:17:37 -0700 (PDT) From: Daniel Vetter To: Intel Graphics Development Date: Thu, 5 Jul 2012 12:17:30 +0200 Message-Id: <1341483450-6385-2-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.7.10.2 In-Reply-To: <1341483450-6385-1-git-send-email-daniel.vetter@ffwll.ch> References: <1341483450-6385-1-git-send-email-daniel.vetter@ffwll.ch> X-Gm-Message-State: ALoCoQnr5SHhMcvydz25ATvC6jcV2Xu9I9qd3CcNEyLAFOE/92UjQM2452ECvPMs8n21jYR/FnrQ Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH 2/2] drm/i915: adjust framebuffer base address on gen4+ X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org The tileoffset register only supports a limited offset in x/y of 4096, so for giant screen configuration with a shared fb we wrap around. Fix this by computing a linear offset in tiles (pages) and only use the tileoffset register to offset within the tile. Signed-Off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_reg.h | 2 +- drivers/gpu/drm/i915/intel_display.c | 47 +++++++++++++++++++++++++++------- 2 files changed, 39 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 871bedc..95d87e3 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2904,7 +2904,7 @@ #define I915_LO_DISPBASE(val) (val & ~DISP_BASEADDR_MASK) #define I915_HI_DISPBASE(val) (val & DISP_BASEADDR_MASK) #define I915_MODIFY_DISPBASE(reg, gfx_addr) \ - (I915_WRITE(reg, gfx_addr | I915_LO_DISPBASE(I915_READ(reg)))) + (I915_WRITE((reg), (gfx_addr) | I915_LO_DISPBASE(I915_READ(reg)))) /* VBIOS flags */ #define SWF00 0x71410 diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 839633c..08d9f8b 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1824,6 +1824,22 @@ void intel_unpin_fb_obj(struct drm_i915_gem_object *obj) i915_gem_object_unpin(obj); } +/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel + * is assumed to be a power-of-two. */ +static unsigned long gen4_compute_dspaddr_offset_xtiled(int *x, int *y, + unsigned int bpp, + unsigned int pitch) +{ + int tile_rows, tiles; + + tile_rows = *y / 8; + *y %= 8; + tiles = *x / (512/bpp); + *x %= 512/bpp; + + return tile_rows * pitch * 8 + tiles * 4096; +} + static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb, int x, int y) { @@ -1882,16 +1898,22 @@ static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb, linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); - if (INTEL_INFO(dev)->gen >= 4) - intel_crtc->dspaddr_offset = 0; - else + if (INTEL_INFO(dev)->gen >= 4) { + intel_crtc->dspaddr_offset = + gen4_compute_dspaddr_offset_xtiled(&x, &y, + fb->bits_per_pixel / 8, + fb->pitches[0]); + linear_offset -= intel_crtc->dspaddr_offset; + } else { intel_crtc->dspaddr_offset = linear_offset; + } DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n", obj->gtt_offset, linear_offset, x, y, fb->pitches[0]); I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); if (INTEL_INFO(dev)->gen >= 4) { - I915_MODIFY_DISPBASE(DSPSURF(plane), obj->gtt_offset); + I915_MODIFY_DISPBASE(DSPSURF(plane), + obj->gtt_offset + intel_crtc->dspaddr_offset); I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); I915_WRITE(DSPLINOFF(plane), linear_offset); } else @@ -1966,12 +1988,17 @@ static int ironlake_update_plane(struct drm_crtc *crtc, I915_WRITE(reg, dspcntr); linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); - intel_crtc->dspaddr_offset = 0; + intel_crtc->dspaddr_offset = + gen4_compute_dspaddr_offset_xtiled(&x, &y, + fb->bits_per_pixel / 8, + fb->pitches[0]); + linear_offset -= intel_crtc->dspaddr_offset; DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n", obj->gtt_offset, linear_offset, x, y, fb->pitches[0]); I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); - I915_MODIFY_DISPBASE(DSPSURF(plane), obj->gtt_offset); + I915_MODIFY_DISPBASE(DSPSURF(plane), + obj->gtt_offset + intel_crtc->dspaddr_offset); I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); I915_WRITE(DSPLINOFF(plane), linear_offset); POSTING_READ(reg); @@ -6080,7 +6107,9 @@ static int intel_gen4_queue_flip(struct drm_device *dev, intel_ring_emit(ring, MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); intel_ring_emit(ring, fb->pitches[0]); - intel_ring_emit(ring, obj->gtt_offset | obj->tiling_mode); + intel_ring_emit(ring, + (obj->gtt_offset + intel_crtc->dspaddr_offset) | + obj->tiling_mode); /* XXX Enabling the panel-fitter across page-flip is so far * untested on non-native modes, so ignore it for now. @@ -6120,7 +6149,7 @@ static int intel_gen6_queue_flip(struct drm_device *dev, intel_ring_emit(ring, MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); - intel_ring_emit(ring, obj->gtt_offset); + intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset); /* Contrary to the suggestions in the documentation, * "Enable Panel Fitter" does not seem to be required when page @@ -6183,7 +6212,7 @@ static int intel_gen7_queue_flip(struct drm_device *dev, intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); - intel_ring_emit(ring, (obj->gtt_offset)); + intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset); intel_ring_emit(ring, (MI_NOOP)); intel_ring_advance(ring); return 0;