From patchwork Mon Jul 16 18:51:56 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Widawsky X-Patchwork-Id: 1201691 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id 3B6553FD9C for ; Mon, 16 Jul 2012 18:55:02 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id ADB109EE99 for ; Mon, 16 Jul 2012 11:55:00 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from cloud01.chad-versace.us (184-106-247-128.static.cloud-ips.com [184.106.247.128]) by gabe.freedesktop.org (Postfix) with ESMTP id 4814E9EB3A for ; Mon, 16 Jul 2012 11:54:02 -0700 (PDT) Received: from localhost (localhost [127.0.0.1]) by cloud01.chad-versace.us (Postfix) with ESMTP id 82954181088; Mon, 16 Jul 2012 18:56:44 +0000 (UTC) X-Virus-Scanned: amavisd-new at static.cloud-ips.com X-Spam-Flag: NO X-Spam-Score: -2.9 X-Spam-Level: X-Spam-Status: No, score=-2.9 tagged_above=-100 required=3.5 tests=[ALL_TRUSTED=-1, BAYES_00=-1.9] autolearn=ham Received: from cloud01.chad-versace.us ([127.0.0.1]) by localhost (cloud01.static.cloud-ips.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 8qjVPW7c8VZu; Mon, 16 Jul 2012 18:56:39 +0000 (UTC) Received: from seagal.jf.intel.com (jfdmzpr02-ext.jf.intel.com [134.134.137.71]) by cloud01.chad-versace.us (Postfix) with ESMTPSA id 3ED8B18107E; Mon, 16 Jul 2012 18:56:39 +0000 (UTC) From: Ben Widawsky To: intel-gfx@lists.freedesktop.org Date: Mon, 16 Jul 2012 11:51:56 -0700 Message-Id: <1342464719-8790-2-git-send-email-ben@bwidawsk.net> X-Mailer: git-send-email 1.7.11.2 In-Reply-To: <1342464719-8790-1-git-send-email-ben@bwidawsk.net> References: <1342464719-8790-1-git-send-email-ben@bwidawsk.net> Cc: Ben Widawsky Subject: [Intel-gfx] [PATCH 1/4] drm/i915: Use HW watchdog for each batch X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org The HW watchdog exists for all the rings. It's just a register, but if we writing in the command stream it has the effect we want of generating interrupts if a given batch is taking too long. Unfortunately, our hardware doesn't support interrupts on the blit ring. We still need the software watchdog for that. Signed-off-by: Ben Widawsky --- drivers/gpu/drm/i915/i915_drv.h | 2 +- drivers/gpu/drm/i915/i915_reg.h | 2 ++ drivers/gpu/drm/i915/intel_ringbuffer.c | 26 +++++++++++++++++++++++++- 3 files changed, 28 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 627fe35..0a13b22 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -430,7 +430,7 @@ typedef struct drm_i915_private { int num_pch_pll; /* For hangcheck timer */ -#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ +#define DRM_I915_HANGCHECK_PERIOD 3000 /* in ms */ struct timer_list hangcheck_timer; int hangcheck_count; uint32_t last_acthd[I915_NUM_RINGS]; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index cc82871..195154b 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -449,6 +449,8 @@ #define RING_ACTHD(base) ((base)+0x74) #define RING_NOPID(base) ((base)+0x94) #define RING_IMR(base) ((base)+0xa8) +#define RING_WATCHDOG_CTL(base) ((base)+0x178) +#define RING_WATCHDOG_THRESH(base) ((base)+0x17c) #define TAIL_ADDR 0x001FFFF8 #define HEAD_WRAP_COUNT 0xFFE00000 #define HEAD_WRAP_ONE 0x00200000 diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index ddc4859..f61b4a0 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -1038,6 +1038,9 @@ static int intel_init_ring_buffer(struct drm_device *dev, goto err_unpin; } + I915_WRITE(RING_WATCHDOG_CTL(ring->mmio_base), UINT_MAX); + I915_WRITE(RING_WATCHDOG_THRESH(ring->mmio_base), UINT_MAX); + ret = ring->init(ring); if (ret) goto err_unmap; @@ -1318,19 +1321,40 @@ static int gen6_ring_flush(struct intel_ring_buffer *ring, return 0; } +#define PERIOD_NS 80 +#define WATCHDOG_TIMEOUT(timeout_ms) (DIV_ROUND_UP(timeout_ms * NSEC_PER_MSEC, PERIOD_NS)) +/* this should be less than the i915 software watchdog */ +#define DEFAULT_WATCHDOG_TIMEOUT WATCHDOG_TIMEOUT(DRM_I915_HANGCHECK_PERIOD / 2) + static int gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 len) { int ret; - ret = intel_ring_begin(ring, 2); + ret = intel_ring_begin(ring, 14); if (ret) return ret; + intel_ring_emit(ring, MI_NOOP); + intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); + intel_ring_emit(ring, RING_WATCHDOG_THRESH(ring->mmio_base)); + intel_ring_emit(ring, DEFAULT_WATCHDOG_TIMEOUT); + intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); + intel_ring_emit(ring, RING_WATCHDOG_CTL(ring->mmio_base)); + intel_ring_emit(ring, 0); + + /* add breadcrumb here */ + intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965); /* bit0-7 is the length on GEN6+ */ intel_ring_emit(ring, offset); + + intel_ring_emit(ring, MI_NOOP); + intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); + intel_ring_emit(ring, RING_WATCHDOG_CTL(ring->mmio_base)); + intel_ring_emit(ring, UINT_MAX); + intel_ring_advance(ring); return 0;