From patchwork Thu Jul 19 20:00:19 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Olivier Galibert X-Patchwork-Id: 1218321 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork2.kernel.org (Postfix) with ESMTP id EA90BDF25A for ; Thu, 19 Jul 2012 20:08:19 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D6C959F0F4 for ; Thu, 19 Jul 2012 13:08:19 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from sasl.smtp.pobox.com (a-pb-sasl-sd.pobox.com [74.115.168.62]) by gabe.freedesktop.org (Postfix) with ESMTP id 5990E9F065; Thu, 19 Jul 2012 13:00:10 -0700 (PDT) Received: from sasl.smtp.pobox.com (unknown [127.0.0.1]) by b-pb-sasl-sd.pobox.com (Postfix) with ESMTP id D6A94B8E4; Thu, 19 Jul 2012 16:00:09 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=pobox.com; h=from:to:cc :subject:date:message-id:in-reply-to:references; s=sasl; bh=IRhL XpJSZ1x1iQItn6n9DzhwAk0=; b=w4aHJQm9VTXORh+x8F0So9ayWgd1x9aAksJ7 dyg2XwhNchvrHH5cJiRQRW5jw+4aWSEdJ6r8Iju7096pDTP9KAi1UVyIAf0LeI+a FrhSYlm4MeA2ifMQIN0/TJsGbTc8M39STMZoMhyWn3xhXSFJOpoFuHbwoEDR22ov ql9wjt0= DomainKey-Signature: a=rsa-sha1; c=nofws; d=pobox.com; h=from:to:cc :subject:date:message-id:in-reply-to:references; q=dns; s=sasl; b= AODCpGo6Z+vwb1O8EBp/VjwyoVWkzgAd6l08sOHYMvLqTMICzZTJw/QNNCseggbQ GR9SpusNjzikgeWMrOQH9iMcN8eYeOJ4uIJy4oR1i/UYSbyJ6/QGD2MCSkZ4OUzH wFV2Qfy8Du5WGZXypE8hikz1Z1IZndAE0T2Y8OVPM88= Received: from b-pb-sasl-sd. (unknown [127.0.0.1]) by b-pb-sasl-sd.pobox.com (Postfix) with ESMTP id B8182B8E2; Thu, 19 Jul 2012 16:00:09 -0400 (EDT) Received: from localhost.localdomain (unknown [82.234.121.82]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by b-pb-sasl-sd.pobox.com (Postfix) with ESMTPSA id DF292B8E1; Thu, 19 Jul 2012 16:00:06 -0400 (EDT) From: Olivier Galibert To: intel-gfx@lists.freedesktop.org, mesa-dev@lists.freedesktop.org Date: Thu, 19 Jul 2012 22:00:19 +0200 Message-Id: <1342728024-15055-5-git-send-email-galibert@pobox.com> X-Mailer: git-send-email 1.7.10.280.gaa39 In-Reply-To: <1342728024-15055-1-git-send-email-galibert@pobox.com> References: <1342728024-15055-1-git-send-email-galibert@pobox.com> X-Pobox-Relay-ID: 57480AA6-D1DC-11E1-9B6D-126B87E41631-92059326!b-pb-sasl-sd.pobox.com Cc: Olivier Galibert Subject: [Intel-gfx] [PATCH 4/9] intel gen4-5: Fix backface/frontface selection when one one color is written to. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Shaders, piglit test ones in particular, may write only to one of gl_FrontColor/gl_BackColor. The standard is unclear on whether the behaviour is defined in that case, but it seems reasonable to support it. The choice done there to pick up whichever color was actually written to. That makes most of the generated piglit tests useless to test the backface selection, but it's simple and it works. Signed-off-by: Olivier Galibert --- src/mesa/drivers/dri/i965/brw_fs.cpp | 9 +++++++++ src/mesa/drivers/dri/i965/brw_wm_pass2.c | 9 +++++++++ 2 files changed, 18 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index 3f98137..3b62952 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp @@ -972,6 +972,15 @@ fs_visitor::calculate_urb_setup() if (c->key.vp_outputs_written & BITFIELD64_BIT(i)) { int fp_index = _mesa_vert_result_to_frag_attrib((gl_vert_result) i); + /* Special case: two-sided vertex option, vertex program + * only writes to the back color. Map it to the + * associated front color location. + */ + if (i >= VERT_RESULT_BFC0 && i <= VERT_RESULT_BFC1 && + ctx->VertexProgram._TwoSideEnabled && + urb_setup[i - VERT_RESULT_BFC0 + FRAG_ATTRIB_COL0] == -1) + fp_index = i - VERT_RESULT_BFC0 + FRAG_ATTRIB_COL0; + /* The back color slot is skipped when the front color is * also written to. In addition, some slots can be * written in the vertex shader and not read in the diff --git a/src/mesa/drivers/dri/i965/brw_wm_pass2.c b/src/mesa/drivers/dri/i965/brw_wm_pass2.c index eacf7c0..48143f3 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_pass2.c +++ b/src/mesa/drivers/dri/i965/brw_wm_pass2.c @@ -96,6 +96,15 @@ static void init_registers( struct brw_wm_compile *c ) if (c->key.vp_outputs_written & BITFIELD64_BIT(j)) { int fp_index = _mesa_vert_result_to_frag_attrib(j); + /* Special case: two-sided vertex option, vertex program + * only writes to the back color. Map it to the + * associated front color location. + */ + if (j >= VERT_RESULT_BFC0 && j <= VERT_RESULT_BFC1 && + intel->ctx.VertexProgram._TwoSideEnabled && + !(c->key.vp_outputs_written & BITFIELD64_BIT(j - VERT_RESULT_BFC0 + VERT_RESULT_COL0))) + fp_index = j - VERT_RESULT_BFC0 + FRAG_ATTRIB_COL0; + nr_interp_regs++; /* The back color slot is skipped when the front color is