From patchwork Wed Jul 25 12:51:43 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 1237341 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork2.kernel.org (Postfix) with ESMTP id AE616DFFCD for ; Wed, 25 Jul 2012 12:52:32 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 49826A0A84 for ; Wed, 25 Jul 2012 05:52:32 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-bk0-f49.google.com (mail-bk0-f49.google.com [209.85.214.49]) by gabe.freedesktop.org (Postfix) with ESMTP id 69E4CA0AB5 for ; Wed, 25 Jul 2012 05:51:52 -0700 (PDT) Received: by bkcji2 with SMTP id ji2so495660bkc.36 for ; Wed, 25 Jul 2012 05:51:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=eZ3wLKcpBAsVpYY8thgAduTY5mp0VU2yA2+xxiSKF94=; b=exnAJbb1lly/3eMPSIWcorms7dhYnDn2Oi6UafGy1ZMjquWIwqs9PWAXXwE0QD3tff Fw8U2torE4IaOOOQOkamGNMPXcfFUibbD7I7i1HXGLhTrsHQp4qTj56P9zO/lo7E5QOg V08mWnBCXHIwiv9oLM/BLA3pIm2n1je3N1XIw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=eZ3wLKcpBAsVpYY8thgAduTY5mp0VU2yA2+xxiSKF94=; b=PKwQmoyMiPhosfYAqfaV9bmoVlit/O5/Jx/aApo0ak6gsV02ouTSk0Jm5NWNgna/Gz S34ryQLa7E93E6Yz3ig0yZNmDXxUXHigZfOvA3BT9kDRqXZZBZEIsN2NPa48LqThpsLW k3kXJ6WV8QwPWw9hfFG+SrJSrYZ95t9WSxTJJx129QVY611DvP0BbCjnjHwaQjsYnqcu lmVF39cvyImD+3i/KqqRNcPvW5RhdBgQUkFzqV0LO1QbSvFrj0ddMtBm+f/BsyPNtXD1 Dqi+FbDeHf3l21zIo4A9UCMzb2bIQHG98HVo6l7XVc8gKC25dLu/RuZ07+SOrrsOpYiM pXgQ== Received: by 10.204.145.82 with SMTP id c18mr11716878bkv.133.1343220711471; Wed, 25 Jul 2012 05:51:51 -0700 (PDT) Received: from aaron.ffwll.local (178-83-130-250.dynamic.hispeed.ch. [178.83.130.250]) by mx.google.com with ESMTPS id 14sm12786595bkq.12.2012.07.25.05.51.49 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 25 Jul 2012 05:51:50 -0700 (PDT) From: Daniel Vetter To: Intel Graphics Development Date: Wed, 25 Jul 2012 14:51:43 +0200 Message-Id: <1343220704-4210-1-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1342803748-25695-1-git-send-email-chris@chris-wilson.co.uk> References: <1342803748-25695-1-git-send-email-chris@chris-wilson.co.uk> X-Gm-Message-State: ALoCoQl6N2dgHDuUPLIRJoQ/B5vJBn+fGb9qQGUbT8/udh3bScmtFGJBRDmY2svnk/23zaetGUK2 Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH 1/2] drm/i915: flush DC writes cached in l3$ on gen7 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org We don't yet use this, but now that we start to look into putting that l3$ we better set the associated flush bit, too. Also add the only other missing PIPE_CONTROL bit #define. Signed-Off-by: Daniel Vetter Reviewed-by: Eric Anholt --- drivers/gpu/drm/i915/i915_reg.h | 2 ++ drivers/gpu/drm/i915/intel_ringbuffer.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 81a3de6..721a981 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -311,6 +311,8 @@ #define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */ #define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9) #define PIPE_CONTROL_NOTIFY (1<<8) +#define PIPE_CONTROL_FLUSH_ENABLE (1<<7) /* gen7+ */ +#define PIPE_CONTROL_DC_CACHE_FLUSH (1<<5) /* gen7+ */ #define PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4) #define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1<<3) #define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1<<2) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 58e6b0e..f52778f 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -228,6 +228,8 @@ gen6_render_ring_flush(struct intel_ring_buffer *ring, flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; + if (IS_GEN7(ring->dev)) + flags |= PIPE_CONTROL_DC_CACHE_FLUSH; /* * Ensure that any following seqno writes only happen when the render * cache is indeed flushed (but only if the caller actually wants that).