From patchwork Wed Jul 25 19:32:09 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 1239461 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id C35DA3FDFB for ; Wed, 25 Jul 2012 19:32:46 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id AF4D0A0DA5 for ; Wed, 25 Jul 2012 12:32:46 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wg0-f43.google.com (mail-wg0-f43.google.com [74.125.82.43]) by gabe.freedesktop.org (Postfix) with ESMTP id 57A019EEDD for ; Wed, 25 Jul 2012 12:32:17 -0700 (PDT) Received: by wgbdr1 with SMTP id dr1so861678wgb.12 for ; Wed, 25 Jul 2012 12:32:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=from:to:cc:subject:date:message-id:x-mailer; bh=qxxkkhspne3OTnDa754MTWH9mgWL+GH5HVKELln/+rQ=; b=apO6E2VYvnhcxspbJuP0oLKJ7bWiNxYeUuUGwPqJPLa34JAJaU7KfuSqi9/CyZAWPG TigAsaog1pyTZHb5ghWReSb1d2blUauzgwYS6cRQ88emzN1szQSjXTT4XMgH1miIgfvR srTCC8+Uo4zxdgBR7mgyBRnWRS5fSo5Q2Zk4g= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:x-gm-message-state; bh=qxxkkhspne3OTnDa754MTWH9mgWL+GH5HVKELln/+rQ=; b=WuhxeAqXUwV2HiXHuwVLByNmhd9DNXkgG5TNoX/SCA+NfUWuqlMLIjtyhT2flgtBi0 G6zI0UbMrrg+sQiQMb3wpke1CtIiH5qjdugRhIqM2W1OpFotJu7Cv6WDCAHDGgiYbddc A59DX3+M6nUcdgrVp0UnGr1rLvrh/NmU6mIsy7Fd4sNrvBIigszhRNR12zkyLcOLluwW rwYT1T3udqeZy2Qs3FYK3zpqd9tKGPei1BT6mpCLa9KpA/SphO+Dtryv/rN+3PaP7TLl JDcwMJj57jYkavaEXG+8fU4ekwqqnYmdmksvTG+gVvz7COuvT5j4mmWni4T3gVdkJnsn m8Ig== Received: by 10.180.74.33 with SMTP id q1mr7256217wiv.4.1343244736375; Wed, 25 Jul 2012 12:32:16 -0700 (PDT) Received: from bremse.ffwll.local (178-83-130-250.dynamic.hispeed.ch. [178.83.130.250]) by mx.google.com with ESMTPS id y5sm4096086wiw.9.2012.07.25.12.32.14 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 25 Jul 2012 12:32:15 -0700 (PDT) From: Daniel Vetter To: Intel Graphics Development Date: Wed, 25 Jul 2012 21:32:09 +0200 Message-Id: <1343244729-12867-1-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.7.10.4 X-Gm-Message-State: ALoCoQmnbsUJmwKarQHoT4LgXQoGoq3oGHV9C7K/7v7O38FIJ8mkcYkRNoyVtIRJkWUbvoqFJq1X Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH] [CFT] drm/i915: Only set the down rps limit when at the loweset frequency X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org The power docs say that when the gt leaves rc6, it is in the lowest frequency and only about 25 usec later will switch to the frequency selected in GEN6_RPNSWREQ. If the downclock limit expires in that window and the down limit is set to the lowest possible frequency, the hw will not send the down interrupt. Which leads to a too high gpu clock and wasted power. Chris Wilson already worked on this with commit 7b9e0ae6da0a7eaf2680a1a788f08df123724f3b Author: Chris Wilson Date: Sat Apr 28 08:56:39 2012 +0100 drm/i915: Always update RPS interrupts thresholds along with frequency but got the logic inverted: The current code set the down limit as long as we haven't reached it. Instead of only once with reached the lowest frequency. Note that we can't always set the downclock limit to 0, because otherwise the hw will keep on bugging us with downclock request irqs once the lowest level is reached. For similar reasons also always set the upclock limit, otherwise the hw might poke us again with interrupts. Signed-Off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_pm.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index d0ce2a5..c2a7c9f 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -2275,13 +2275,18 @@ void gen6_set_rps(struct drm_device *dev, u8 val) limits = 0; if (val >= dev_priv->max_delay) val = dev_priv->max_delay; - else - limits |= dev_priv->max_delay << 24; - - if (val <= dev_priv->min_delay) + limits |= dev_priv->max_delay << 24; + + /* Only set the down limit when we've reached the lowest level to avoid + * getting more interrupts, otherwise leave this clear. This prevents a + * race in the hw when coming out of rc6: There's a tiny window where + * the hw runs at the minimal clock before selecting the desired + * frequency, if the down threshold expires in that window we will not + * receive a down interrupt. */ + if (val <= dev_priv->min_delay) { val = dev_priv->min_delay; - else limits |= dev_priv->min_delay << 16; + } if (val == dev_priv->cur_delay) return;