From patchwork Thu Jul 26 18:48:56 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 1244991 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id 8AA503FC33 for ; Thu, 26 Jul 2012 20:24:25 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 529FD9EF22 for ; Thu, 26 Jul 2012 13:24:25 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-we0-f177.google.com (mail-we0-f177.google.com [74.125.82.177]) by gabe.freedesktop.org (Postfix) with ESMTP id 44F5F9EB84 for ; Thu, 26 Jul 2012 12:56:50 -0700 (PDT) Received: by mail-we0-f177.google.com with SMTP id r3so1738755wey.36 for ; Thu, 26 Jul 2012 12:56:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=n00D++LfepDv5yj8d+KOMjDJX0ijKna6vVpE1BDwdNY=; b=d4mWJOJF1UcsR6a76QM6woUbm9lKMBhorO+FFPbn3qeK53SFZAPhvlyKc6nZqmo+cO i4loleApKY4SywHHLHeRbOLDSinRAl7D9FI3k+LFVhbd/vKo6HvnOZ8c23/2aaX3060C gNSA7g62wF961377n8noNU/fagO47bK25ii68= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=n00D++LfepDv5yj8d+KOMjDJX0ijKna6vVpE1BDwdNY=; b=P3LQtZjjg5Do4HgTBF6FLjRq/CUwWCFbloyO8IRglpcVHKu0yBQi8G5N1urqoka7Lt KMa3rhRJNTPUv8UpryuD2gwyFV3Auypbx4iOHBf+MTd68BUuMOYE2jL6L516ptNqFju4 BvqZNZpeI6Obh0xCJq5xUMTevE649cnIpZkaP30w7NcdN9jSgt3Kuv7+c0841HV1fHW3 zQqBKeMYccofO15AJWHfso4Zpig6hDxb92AZoM9a3S0j5EICY5iYbcJ09pdNqX6J4Llg zxjQ2TL54ZLf73QkS8P/BtI482qRsyXHxyJM5VE90roeUfVfD/pWz6whCEo4/JWAQnjj XrlA== Received: by 10.180.106.137 with SMTP id gu9mr58914wib.20.1343332610046; Thu, 26 Jul 2012 12:56:50 -0700 (PDT) Received: from wespe.ffwll.local (178-83-130-250.dynamic.hispeed.ch. [178.83.130.250]) by mx.google.com with ESMTPS id fr4sm391403wib.8.2012.07.26.12.56.48 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 26 Jul 2012 12:56:49 -0700 (PDT) From: Daniel Vetter To: Intel Graphics Development Date: Thu, 26 Jul 2012 20:48:56 +0200 Message-Id: <1343328581-2324-32-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1343328581-2324-1-git-send-email-daniel.vetter@ffwll.ch> References: <1343328581-2324-1-git-send-email-daniel.vetter@ffwll.ch> X-Gm-Message-State: ALoCoQnALrnkBMVgxmD6iavjQPiGSCvmpFfJDwqvS2IqcEcD2j6hbmN6gp7Qfzrh5aDuKayNFC6F Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH 31/76] drm/i915/dp: implement get_hw_state X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Also add some macros to make the pipe computation a bit easier. v2: I've mixed up the CPT and !CPT PORT_TO_PIPE macro variants ... Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_reg.h | 2 ++ drivers/gpu/drm/i915/intel_dp.c | 50 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 52 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 1310caa..dd6bd7a 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4029,6 +4029,8 @@ #define PORT_TRANS_C_SEL_CPT (2<<29) #define PORT_TRANS_SEL_MASK (3<<29) #define PORT_TRANS_SEL_CPT(pipe) ((pipe) << 29) +#define PORT_TO_PIPE(val) (((val) & (1<<30)) >> 30) +#define PORT_TO_PIPE_CPT(val) (((val) & PORT_TRANS_SEL_MASK) >> 29) #define TRANS_DP_CTL_A 0xe0300 #define TRANS_DP_CTL_B 0xe1300 diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 7a65f37..b201c7e 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -1246,6 +1246,54 @@ static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) } } +static bool intel_dp_get_hw_state(struct intel_encoder *encoder, + enum pipe *pipe) +{ + struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); + struct drm_device *dev = encoder->base.dev; + struct drm_i915_private *dev_priv = dev->dev_private; + u32 tmp = I915_READ(intel_dp->output_reg); + + if (!(tmp & DP_PORT_EN)) + return false; + + if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) { + *pipe = PORT_TO_PIPE_CPT(tmp); + } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) { + *pipe = PORT_TO_PIPE(tmp); + } else { + u32 trans_sel; + u32 trans_dp; + int i; + + switch (intel_dp->output_reg) { + case PCH_DP_B: + trans_sel = TRANS_DP_PORT_SEL_B; + break; + case PCH_DP_C: + trans_sel = TRANS_DP_PORT_SEL_C; + break; + case PCH_DP_D: + trans_sel = TRANS_DP_PORT_SEL_D; + break; + default: + return true; + } + + for_each_pipe(i) { + trans_dp = I915_READ(TRANS_DP_CTL(i)); + if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) { + *pipe = i; + return true; + } + } + } + + DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", intel_dp->output_reg); + + return true; +} + static void intel_disable_dp(struct intel_encoder *encoder) { struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); @@ -2484,6 +2532,8 @@ intel_dp_init(struct drm_device *dev, int output_reg, enum port port) intel_encoder->enable = intel_enable_dp; intel_encoder->disable = intel_disable_dp; + intel_encoder->get_hw_state = intel_dp_get_hw_state; + intel_connector->get_hw_state = intel_connector_get_hw_state; /* Set up the DDC bus. */ switch (port) {