From patchwork Fri Aug 17 21:35:42 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paulo Zanoni X-Patchwork-Id: 1339631 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork2.kernel.org (Postfix) with ESMTP id 46906DF280 for ; Fri, 17 Aug 2012 21:37:04 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2D797A0F1D for ; Fri, 17 Aug 2012 14:37:04 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-yx0-f177.google.com (mail-yx0-f177.google.com [209.85.213.177]) by gabe.freedesktop.org (Postfix) with ESMTP id EA9E4A0F1D for ; Fri, 17 Aug 2012 14:35:44 -0700 (PDT) Received: by yenq9 with SMTP id q9so4718006yen.36 for ; Fri, 17 Aug 2012 14:35:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=oSHIXPmck+5ncC+7JHkWiR+mUzESdMsv+xHRsmAIwXg=; b=jqq+mhsmIT1yJhfE8/jlwFphmwnc+h9GFKyj+XdeMwX0ij603mjt7Uxpt9Ly1kARwb /mAo8OVATdvd8Gcj8i2ApkK/OMi0MFLE8o14RY0sttEXe2A+cCcCkyon7Kb7Su7NrmG2 VVRr4zIg6FB3uEZvwpQ6AwtkSdhhHB/3JYB7qeUPCDKxn7G0eDMhnHxzBR+Hhm0FkjcB PwFMmbSeLY/zHEHlIqD6wdOT/nQLoYdFZDNlF1urbaipLgknZWWwvkQkhUMRz8JzMi8s aBsgrqb47g/gtLefIQJ77UH8MZq8ERL24YONaag6q6m4T85UefL35nMH0v4QW4Y/2cgD pi2A== Received: by 10.236.125.133 with SMTP id z5mr10686285yhh.121.1345239344281; Fri, 17 Aug 2012 14:35:44 -0700 (PDT) Received: from vicky.domain.invalid ([189.114.188.159]) by mx.google.com with ESMTPS id h8sm7958600ank.9.2012.08.17.14.35.42 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 17 Aug 2012 14:35:43 -0700 (PDT) From: Paulo Zanoni To: intel-gfx@lists.freedesktop.org Date: Fri, 17 Aug 2012 18:35:42 -0300 Message-Id: <1345239344-9968-3-git-send-email-przanoni@gmail.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1345239344-9968-1-git-send-email-przanoni@gmail.com> References: <1345239344-9968-1-git-send-email-przanoni@gmail.com> Cc: Paulo Zanoni Subject: [Intel-gfx] [PATCH 2/4] drm/i915: add workarounds directly to gen6_render_ring_flush X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org From: Paulo Zanoni Since gen 7+ now run the new gen7_render_ring_flush function. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_ringbuffer.c | 21 ++++++--------------- 1 file changed, 6 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 32e3034..dc5272b 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -218,6 +218,11 @@ gen6_render_ring_flush(struct intel_ring_buffer *ring, u32 scratch_addr = pc->gtt_offset + 128; int ret; + /* Force SNB workarounds for PIPE_CONTROL flushes */ + ret = intel_emit_post_sync_nonzero_flush(ring); + if (ret) + return ret; + /* Just flush everything. Experiments have shown that reducing the * number of bits based on the write domains has little performance * impact. @@ -305,20 +310,6 @@ gen7_render_ring_flush(struct intel_ring_buffer *ring, return 0; } -static int -gen6_render_ring_flush__wa(struct intel_ring_buffer *ring, - u32 invalidate_domains, u32 flush_domains) -{ - int ret; - - /* Force SNB workarounds for PIPE_CONTROL flushes */ - ret = intel_emit_post_sync_nonzero_flush(ring); - if (ret) - return ret; - - return gen6_render_ring_flush(ring, invalidate_domains, flush_domains); -} - static void ring_write_tail(struct intel_ring_buffer *ring, u32 value) { @@ -1435,7 +1426,7 @@ int intel_init_render_ring_buffer(struct drm_device *dev) ring->add_request = gen6_add_request; ring->flush = gen7_render_ring_flush; if (INTEL_INFO(dev)->gen == 6) - ring->flush = gen6_render_ring_flush__wa; + ring->flush = gen6_render_ring_flush; ring->irq_get = gen6_ring_get_irq; ring->irq_put = gen6_ring_put_irq; ring->irq_enable_mask = GT_USER_INTERRUPT;