From patchwork Fri Aug 17 21:35:43 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paulo Zanoni X-Patchwork-Id: 1339641 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id A65CF3FC81 for ; Fri, 17 Aug 2012 21:37:41 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8F5C9A0EFA for ; Fri, 17 Aug 2012 14:37:41 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-yx0-f177.google.com (mail-yx0-f177.google.com [209.85.213.177]) by gabe.freedesktop.org (Postfix) with ESMTP id 56D6DA0F2F for ; Fri, 17 Aug 2012 14:35:47 -0700 (PDT) Received: by mail-yx0-f177.google.com with SMTP id q9so4718006yen.36 for ; Fri, 17 Aug 2012 14:35:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=SM3qFAmhlzWbCCoi73KQ7RuiGDqBSNnaHVqUpwEIX4Q=; b=NT2Bbskllvm/9YDiFO+fpFG9lFxw41S8k8oiQYW9ON9iD7m30wkXpCUgWbtCsT890/ wR657nRvtmltaBuWskwZZAjE9a4/0FTAUCiC9z6XniEmzWaMfmCId/Kw6au6EOSzRJ8d sgeL7nQahQkTpzGpv/YLiGvlbP54RcxmAnM6Gu8BUeHDdY/RVel9ULpo+nW/OTdB35lf COnNE0fitidPw1zUyV6fJV3wc1nZSfar/O5SM6UynxJkE1djZ1RqzDODz0J9K9sQVYAX BpT7I2pHcDSpNUPzqhUOWfp2WUCLZqwG6K3LP/thKDecVeWaWUlVWQSQeDJVSW55V9qd fXyw== Received: by 10.236.176.71 with SMTP id a47mr10681211yhm.43.1345239347163; Fri, 17 Aug 2012 14:35:47 -0700 (PDT) Received: from vicky.domain.invalid ([189.114.188.159]) by mx.google.com with ESMTPS id h8sm7958600ank.9.2012.08.17.14.35.45 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 17 Aug 2012 14:35:46 -0700 (PDT) From: Paulo Zanoni To: intel-gfx@lists.freedesktop.org Date: Fri, 17 Aug 2012 18:35:43 -0300 Message-Id: <1345239344-9968-4-git-send-email-przanoni@gmail.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1345239344-9968-1-git-send-email-przanoni@gmail.com> References: <1345239344-9968-1-git-send-email-przanoni@gmail.com> Cc: Paulo Zanoni Subject: [Intel-gfx] [PATCH 3/4] drm/i915: add workaround to gen7_render_ring_flush X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org From: Paulo Zanoni The combination of this commit + the next one will prevent a lot of gpu hangs. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_ringbuffer.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index dc5272b..9895a6e 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -263,6 +263,25 @@ gen6_render_ring_flush(struct intel_ring_buffer *ring, } static int +gen7_render_ring_cs_stall_wa(struct intel_ring_buffer *ring) +{ + int ret; + + ret = intel_ring_begin(ring, 4); + if (ret) + return ret; + + intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); + intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | + PIPE_CONTROL_STALL_AT_SCOREBOARD); + intel_ring_emit(ring, 0); + intel_ring_emit(ring, 0); + intel_ring_advance(ring); + + return 0; +} + +static int gen7_render_ring_flush(struct intel_ring_buffer *ring, u32 invalidate_domains, u32 flush_domains) { @@ -295,6 +314,11 @@ gen7_render_ring_flush(struct intel_ring_buffer *ring, * TLB invalidate requires a post-sync write. */ flags |= PIPE_CONTROL_QW_WRITE; + + /* Workaround: we must issue a pipe_control with CS-stall bit + * set before a pipe_control command that has the state cache + * invalidate bit set. */ + gen7_render_ring_cs_stall_wa(ring); } ret = intel_ring_begin(ring, 4);