From patchwork Fri Aug 17 21:35:44 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paulo Zanoni X-Patchwork-Id: 1339651 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id 6237E3FC81 for ; Fri, 17 Aug 2012 21:38:17 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4724BA0F1D for ; Fri, 17 Aug 2012 14:38:17 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-gh0-f177.google.com (mail-gh0-f177.google.com [209.85.160.177]) by gabe.freedesktop.org (Postfix) with ESMTP id E5151A0F0A for ; Fri, 17 Aug 2012 14:35:49 -0700 (PDT) Received: by ghbf20 with SMTP id f20so4716640ghb.36 for ; Fri, 17 Aug 2012 14:35:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=yEcyrJjvH0DgojtqRW2RZsSwfub5Ng3wV2XGf1NYM04=; b=cvOHv69r3kWX2/Eub9w2tbUtYZaw9Z0u2jtd1RZz3bok7e3bQBftVmJa4LTwvZaatx yMoJXnlQClquwnXz2PPG6txH3H43bFhgA3ql9TI+nz2oFqPWtVqYv56nSZUizmIHWjEn +wwZ2aUCVFoKWrpAYjrr5flqZ/CA4STJIhzg/O8FMQm003gRvSmHPy3My+yYEnVrtQ72 r3rknNlMpE0p5yOfjz7+4Or8A2cBAaPR5ef1A0tJtdENqHKKKCiR+zrEPS9vdesxSWuL eVN5xwgIXr/1sVK5uq6Z/dNlyuKVJ4c6fIv06HL7xQEYzMhPXHXu0AiHy0KSaqxskReR 6RmA== Received: by 10.236.161.165 with SMTP id w25mr10751135yhk.22.1345239349479; Fri, 17 Aug 2012 14:35:49 -0700 (PDT) Received: from vicky.domain.invalid ([189.114.188.159]) by mx.google.com with ESMTPS id h8sm7958600ank.9.2012.08.17.14.35.48 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 17 Aug 2012 14:35:49 -0700 (PDT) From: Paulo Zanoni To: intel-gfx@lists.freedesktop.org Date: Fri, 17 Aug 2012 18:35:44 -0300 Message-Id: <1345239344-9968-5-git-send-email-przanoni@gmail.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1345239344-9968-1-git-send-email-przanoni@gmail.com> References: <1345239344-9968-1-git-send-email-przanoni@gmail.com> Cc: Paulo Zanoni Subject: [Intel-gfx] [PATCH 4/4] drm/i915: add one more workaround to gen7_render_ring_flush X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org From: Paulo Zanoni The combination of this commit + the previous one prevents the dozens of GPU hangs I'm seeing on my gen 7.5 machine. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_ringbuffer.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 9895a6e..7c0bc96 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -290,6 +290,15 @@ gen7_render_ring_flush(struct intel_ring_buffer *ring, u32 scratch_addr = pc->gtt_offset + 128; int ret; + /* + * Ensure that any following seqno writes only happen when the render + * cache is indeed flushed. + * The documentation also mentions that every 4th PIPE_CONTROL command + * (except the ones with only read-cache invalidate bits set) must have + * the CS_STALL bit set. + */ + flags |= PIPE_CONTROL_CS_STALL; + /* Just flush everything. Experiments have shown that reducing the * number of bits based on the write domains has little performance * impact. @@ -297,11 +306,6 @@ gen7_render_ring_flush(struct intel_ring_buffer *ring, if (flush_domains) { flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; - /* - * Ensure that any following seqno writes only happen - * when the render cache is indeed flushed. - */ - flags |= PIPE_CONTROL_CS_STALL; } if (invalidate_domains) { flags |= PIPE_CONTROL_TLB_INVALIDATE;