From patchwork Sun Aug 19 19:12:40 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 1344961 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork2.kernel.org (Postfix) with ESMTP id 4A637DF264 for ; Sun, 19 Aug 2012 20:36:33 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 44E28A1041 for ; Sun, 19 Aug 2012 13:36:33 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wi0-f177.google.com (mail-wi0-f177.google.com [209.85.212.177]) by gabe.freedesktop.org (Postfix) with ESMTP id 03C31A0FA0 for ; Sun, 19 Aug 2012 13:20:44 -0700 (PDT) Received: by mail-wi0-f177.google.com with SMTP id hn17so2755791wib.12 for ; Sun, 19 Aug 2012 13:20:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=PCS5fpf82q6N9SnMhge4XcyGk307ov7UbQ25EwfyWPY=; b=YVAQ2nhqFY2DqCB3dALh+EX2Kk2Vos7qzIRmeOR49VljdEf6PkMVRqQ9PJ3hW8SmJ1 rl83aPLCy2fMb+vbzwFypBd1epuHsPPTodBjlegpnBaSViDCGh0R+mTlJbU7biFR8qKX +VyBL0uwiMu7a8CIzA+wrBGreJkzN3pYjYUDg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=PCS5fpf82q6N9SnMhge4XcyGk307ov7UbQ25EwfyWPY=; b=jD6H4nESES6b+cHTZvuLjAnGB89KsAPodujxV0ybxK18b5SFgSYENEA3+pPI8t+xXu qUC2Sdx/LF9D5hYQzggbsgIdTWKUZdQXjuoLqAVRW+FFsbt2ps7/QoXJZL+OekBe4D80 FoXGpuXlKwSb5qYdvEZ8SPRLjd+TiyAYdAZZOCmQNO9oW6bZmYxBjddt0bTOT6++NhdV YUKsjrN2XLKpV96hDkKUBWWDEOwOkdRmPNzRYDDYUsFYLwM49sTSwBduIbzITd33v7Zg qma28IoXIxF9TdsLhG4qBbxch83K9dX+iZhCPx6B+t9rJL5suDSXsr3tkbPyWA+VpfkO Lscg== Received: by 10.216.241.198 with SMTP id g48mr5058403wer.192.1345407644695; Sun, 19 Aug 2012 13:20:44 -0700 (PDT) Received: from wespe.ffwll.local (178-83-130-250.dynamic.hispeed.ch. [178.83.130.250]) by mx.google.com with ESMTPS id fu8sm24194367wib.5.2012.08.19.13.20.43 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 19 Aug 2012 13:20:44 -0700 (PDT) From: Daniel Vetter To: Intel Graphics Development Date: Sun, 19 Aug 2012 21:12:40 +0200 Message-Id: <1345403595-9678-24-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.7.11.2 In-Reply-To: <1345403595-9678-1-git-send-email-daniel.vetter@ffwll.ch> References: <1345403595-9678-1-git-send-email-daniel.vetter@ffwll.ch> X-Gm-Message-State: ALoCoQm1cO0OWycX1KAmTEVgUs5VtefgJwpvQ3Y+dY0wDM9rjNEvMnT3oesb+NycMSNIYaZNzqfW Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH 23/58] drm/i915/dp: implement get_hw_state X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Also add some macros to make the pipe computation a bit easier. v2: I've mixed up the CPT and !CPT PORT_TO_PIPE macro variants ... Signed-off-by: Daniel Vetter Reviewed-by: Jesse Barnes --- drivers/gpu/drm/i915/i915_reg.h | 2 ++ drivers/gpu/drm/i915/intel_dp.c | 50 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 52 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index fd6a26a..1e5f77a 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4029,6 +4029,8 @@ #define PORT_TRANS_C_SEL_CPT (2<<29) #define PORT_TRANS_SEL_MASK (3<<29) #define PORT_TRANS_SEL_CPT(pipe) ((pipe) << 29) +#define PORT_TO_PIPE(val) (((val) & (1<<30)) >> 30) +#define PORT_TO_PIPE_CPT(val) (((val) & PORT_TRANS_SEL_MASK) >> 29) #define TRANS_DP_CTL_A 0xe0300 #define TRANS_DP_CTL_B 0xe1300 diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index ff993a0..e3928b9 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -1250,6 +1250,54 @@ static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) } } +static bool intel_dp_get_hw_state(struct intel_encoder *encoder, + enum pipe *pipe) +{ + struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); + struct drm_device *dev = encoder->base.dev; + struct drm_i915_private *dev_priv = dev->dev_private; + u32 tmp = I915_READ(intel_dp->output_reg); + + if (!(tmp & DP_PORT_EN)) + return false; + + if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) { + *pipe = PORT_TO_PIPE_CPT(tmp); + } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) { + *pipe = PORT_TO_PIPE(tmp); + } else { + u32 trans_sel; + u32 trans_dp; + int i; + + switch (intel_dp->output_reg) { + case PCH_DP_B: + trans_sel = TRANS_DP_PORT_SEL_B; + break; + case PCH_DP_C: + trans_sel = TRANS_DP_PORT_SEL_C; + break; + case PCH_DP_D: + trans_sel = TRANS_DP_PORT_SEL_D; + break; + default: + return true; + } + + for_each_pipe(i) { + trans_dp = I915_READ(TRANS_DP_CTL(i)); + if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) { + *pipe = i; + return true; + } + } + } + + DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", intel_dp->output_reg); + + return true; +} + static void intel_disable_dp(struct intel_encoder *encoder) { struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); @@ -2486,6 +2534,8 @@ intel_dp_init(struct drm_device *dev, int output_reg, enum port port) intel_encoder->enable = intel_enable_dp; intel_encoder->disable = intel_disable_dp; + intel_encoder->get_hw_state = intel_dp_get_hw_state; + intel_connector->get_hw_state = intel_connector_get_hw_state; /* Set up the DDC bus. */ switch (port) {