From patchwork Thu Sep 6 07:10:02 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 1412501 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id D51BF3FC85 for ; Thu, 6 Sep 2012 08:19:51 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BAFEC9F4E5 for ; Thu, 6 Sep 2012 01:19:51 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-bk0-f49.google.com (mail-bk0-f49.google.com [209.85.214.49]) by gabe.freedesktop.org (Postfix) with ESMTP id DFDC69EDD9 for ; Thu, 6 Sep 2012 01:17:28 -0700 (PDT) Received: by mail-bk0-f49.google.com with SMTP id ji2so643797bkc.36 for ; Thu, 06 Sep 2012 01:17:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=ZKUZNzzHEhIQ8zSQUYsVzTlkNDq1xobZOugeIj47UaI=; b=J66YZc69kqNyPq5v/b8UM0nUcDf1cj5h9irJ3wXKe/kI1CwALizzEjKy5+LYMDPExV j+7d5E0PuKGNvZ102Cwtyi9lXXra7dkfsvOvwlUuGJ3EEkKDHzkodRS+IECsQaBigEVj sKUfQwVsaRwhSQ188qAtzblkWjxUQpyVyRLsM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=ZKUZNzzHEhIQ8zSQUYsVzTlkNDq1xobZOugeIj47UaI=; b=Bj8P17NEA4ctwX3ULd1oboSVN5WXqSZuOnWQHdSS1IBfeH9gYu7cHglEfTJUYBK8Le Gi9/OWIPqCsSBz6UjUS9g/LjtW4tLR7Wsmu3c028Usb/0dfbbKaaJzjNfsRwyxihLlp1 MMX5/5rvEJ7t+R+ubBeRWRU2xRK2q2Oyp24wZ2dyOoT0X6Kp7qIsdoMK4FFMBkeTk4FO hQjZOSgRxsH5+8fRVPMas3Y1sLZNi+MQ27/4MJ/t5l4TzGDIZgWcbee2sBcnCwR77ajV 1TTFutr/dbvHe9GCobveiENNVu57IjQdHfL65tlQ3HNSmnCrf++CczUiiBAPipvoDlQu DazA== Received: by 10.204.10.92 with SMTP id o28mr357846bko.39.1346919448387; Thu, 06 Sep 2012 01:17:28 -0700 (PDT) Received: from wespe.ffwll.local (178-83-130-250.dynamic.hispeed.ch. [178.83.130.250]) by mx.google.com with ESMTPS id hg13sm485182bkc.7.2012.09.06.01.17.26 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 06 Sep 2012 01:17:27 -0700 (PDT) From: Daniel Vetter To: Intel Graphics Development Date: Thu, 6 Sep 2012 09:10:02 +0200 Message-Id: <1346915402-9399-4-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.7.11.2 In-Reply-To: <1346915402-9399-1-git-send-email-daniel.vetter@ffwll.ch> References: <1346915402-9399-1-git-send-email-daniel.vetter@ffwll.ch> X-Gm-Message-State: ALoCoQmAVQ5lLWwgOtDD7nvtq32CK27CYcl7n0bqzNL0w7IKT9DrzIsJx/sFsDCOX+XyD/Yys7Ck Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH 4/4] drm/i915: use gmbus irq to wait for gmbus idle X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org GMBUS_ACTIVE has inverted sense and so doesn't fit into the wait_hw_status helper, hence create a new gmbus_wait_idle functions. Also, we only care about the idle irq event and nothing else, which allows us to use the wait_event_timeout helper directly without jumping through hoops to catch NAKs. Since gen2/3 don't have gmbus interrupts, handle them separately with the old wait_for macro. This shaves another few ms off reading EDID from a hdmi screen on my testbox here. EDID reading with interrupt driven gmbus is now as fast as with busy-looping gmbus at 28 ms here (with negligible cpu overhead). Signed-off-by: Daniel Vetter Reviewed-by: Chris Wilson --- drivers/gpu/drm/i915/intel_i2c.c | 32 ++++++++++++++++++++++++++++---- 1 file changed, 28 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c index 86f2b8c..faf85b3 100644 --- a/drivers/gpu/drm/i915/intel_i2c.c +++ b/drivers/gpu/drm/i915/intel_i2c.c @@ -204,6 +204,7 @@ intel_gpio_setup(struct intel_gmbus *bus, u32 pin) algo->data = bus; } +#define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 4) static int gmbus_wait_hw_status(struct drm_i915_private *dev_priv, u32 gmbus2_status, @@ -239,6 +240,31 @@ gmbus_wait_hw_status(struct drm_i915_private *dev_priv, } static int +gmbus_wait_idle(struct drm_i915_private *dev_priv) +{ + int ret; + int reg_offset = dev_priv->gpio_mmio_base; + +#define C ((I915_READ(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0) + + if (!HAS_GMBUS_IRQ(dev_priv->dev)) + return wait_for(C, 10); + + /* Important: The hw handles only the first bit, so set only one! */ + I915_WRITE(GMBUS4 + reg_offset, GMBUS_IDLE_EN); + + ret = wait_event_timeout(dev_priv->gmbus_wait_queue, C, 10); + + I915_WRITE(GMBUS4 + reg_offset, 0); + + if (ret) + return 0; + else + return -ETIMEDOUT; +#undef C +} + +static int gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg, u32 gmbus1_index) { @@ -405,8 +431,7 @@ gmbus_xfer(struct i2c_adapter *adapter, * We will re-enable it at the start of the next xfer, * till then let it sleep. */ - if (wait_for((I915_READ(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0, - 10)) { + if (gmbus_wait_idle(dev_priv)) { DRM_DEBUG_KMS("GMBUS [%s] timed out waiting for idle\n", adapter->name); ret = -ETIMEDOUT; @@ -430,8 +455,7 @@ clear_err: * it's slow responding and only answers on the 2nd retry. */ ret = -ENXIO; - if (wait_for((I915_READ(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0, - 10)) { + if (gmbus_wait_idle(dev_priv)) { DRM_DEBUG_KMS("GMBUS [%s] timed out after NAK\n", adapter->name); ret = -ETIMEDOUT;