From patchwork Thu Sep 6 20:09:35 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 1417941 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id 006413FC71 for ; Thu, 6 Sep 2012 21:19:32 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id F378CA0D8B for ; Thu, 6 Sep 2012 14:19:31 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wi0-f177.google.com (mail-wi0-f177.google.com [209.85.212.177]) by gabe.freedesktop.org (Postfix) with ESMTP id 081EAA0D9D for ; Thu, 6 Sep 2012 14:16:57 -0700 (PDT) Received: by wibhn17 with SMTP id hn17so1546383wib.12 for ; Thu, 06 Sep 2012 14:16:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=from:to:cc:subject:date:message-id:x-mailer; bh=R72qdcIeTg1Y9guzyRA0bemdcBQryM8JodsXFjzVC14=; b=ZZmdHiBBS2C1t2RheA6cHn96EBekp1hkqx/tLzSxmUlLU5kRQN8lugWJAxEv5i7CIv 2YvgiWKFgy8y8LXOnnlImM+f9+TUJWTadekR4oxG+5GgMAbxRn1iF0+fBmuBGM1k7C7K DO46OVU4msSkTBNBZgXaFSPJzOT8DB68UMozY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:x-gm-message-state; bh=R72qdcIeTg1Y9guzyRA0bemdcBQryM8JodsXFjzVC14=; b=lOizjWaSxDvMD1v1hGi343OcAmg4GlmYF2FfvWGJUFSZ9Xdglh/JjrGLDpSC+oo0Fw oQGQf0DAZGIlR38M5G1jKXqyfBWv5lDflf1ZihoCIKN2ZiIN85UTGYIOtXTbfcGHZCWR mhWhrZWyDAv61henjK59M6xS/QV5/MY2LNU+GydN90i4PYUgQ1NuIugLc/oxMFS4OhwP jUscaMV+zBZkkYgGuh7VKnlgI3CJoYNJhqzL5vsVUvF3XgaA8jWx1vjRZeMN0HfykmOd Oe6OaG2AL90XZwEy5LOCAl/bKv1opwBEAvlErS6ia/sApVhDjFVPkKeXrzGbbkjI3AG+ GJBg== Received: by 10.180.19.166 with SMTP id g6mr7437558wie.13.1346966217166; Thu, 06 Sep 2012 14:16:57 -0700 (PDT) Received: from wespe.ffwll.local (178-83-130-250.dynamic.hispeed.ch. [178.83.130.250]) by mx.google.com with ESMTPS id k2sm8573867wiz.7.2012.09.06.14.16.55 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 06 Sep 2012 14:16:56 -0700 (PDT) From: Daniel Vetter To: Intel Graphics Development Date: Thu, 6 Sep 2012 22:09:35 +0200 Message-Id: <1346962175-7356-1-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.7.11.2 X-Gm-Message-State: ALoCoQmtnGu0/CifKjwLq4NQhLh7qJ+9V/AymufQgewdhLFPTy8bIOdibSuNlV0KyOE4R860pYWl Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH] drm/i915: fixup the plane->pipe fixup code X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org We need to check whether the _other plane is on our pipe, not whether our plane is on the other pipe. Otherwise if not both pipes/planes are active, we won't properly clean up the mess and set up our desired plane->pipe mapping. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=51265 Tested-by: Vladyslav Shtabovenko Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 28 ++++++++++++++++++---------- 1 file changed, 18 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index fd9c275..ce9b247 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -7994,11 +7994,27 @@ static void intel_enable_pipe_a(struct drm_device *dev) } +static bool +intel_check_plane_mapping(struct intel_crtc *crtc) +{ + struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; + u32 reg, val; + + reg = DSPCNTR(!crtc->plane); + val = I915_READ(reg); + + if ((val & DISPLAY_PLANE_ENABLE) == 0 && + (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) + return false; + + return true; +} + static void intel_sanitize_crtc(struct intel_crtc *crtc) { struct drm_device *dev = crtc->base.dev; struct drm_i915_private *dev_priv = dev->dev_private; - u32 reg, val; + u32 reg; /* Clear any frame start delays used for debugging left by the BIOS */ reg = PIPECONF(crtc->pipe); @@ -8006,17 +8022,10 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc) /* We need to sanitize the plane -> pipe mapping first because this will * disable the crtc (and hence change the state) if it is wrong. */ - if (!HAS_PCH_SPLIT(dev)) { + if (!HAS_PCH_SPLIT(dev) && !intel_check_plane_mapping(crtc)) { struct intel_connector *connector; bool plane; - reg = DSPCNTR(crtc->plane); - val = I915_READ(reg); - - if ((val & DISPLAY_PLANE_ENABLE) == 0 && - (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) - goto ok; - DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", crtc->base.base.id); @@ -8040,7 +8049,6 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc) WARN_ON(crtc->active); crtc->base.enabled = false; } -ok: if (dev_priv->quirks & QUIRK_PIPEA_FORCE && crtc->pipe == PIPE_A && !crtc->active) {