From patchwork Thu Sep 6 20:15:41 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 1417971 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id D64463FC71 for ; Thu, 6 Sep 2012 21:24:58 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CA48AA0D8F for ; Thu, 6 Sep 2012 14:24:58 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wi0-f171.google.com (mail-wi0-f171.google.com [209.85.212.171]) by gabe.freedesktop.org (Postfix) with ESMTP id AA8149E829 for ; Thu, 6 Sep 2012 14:23:08 -0700 (PDT) Received: by mail-wi0-f171.google.com with SMTP id hq4so5491846wib.12 for ; Thu, 06 Sep 2012 14:23:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=yX4llbtpMvSfvgxNicHM165TCoNaCxxTdTZzw0dWd3M=; b=bHK0DP3qF5r3qXEnoOA7S4toOQCsdaG1aKomNyMARxRUJDnrejZFplCKSdhJ9EAZv3 XgUVVaa8cswvHgBLCijmc0e8Tmqer9QNzeyIA2pXVhlIAsrWvyOFhIYCl9czoTveFpUc 0noD/WE4WS065ymmDLkPKIPyKhU5x9JmSVBes= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=yX4llbtpMvSfvgxNicHM165TCoNaCxxTdTZzw0dWd3M=; b=O50FGTjA69YSeC2hTZm07QmGS+9NSlAxaLECooT+s7gKniaHqZhEIhX3dkSfZ7r7fE OsQDPAF7yVhSAYueDA16D6zJCMDfuT0L5VvlgLO9quBZ3e+DMneCnZWAtnFoFjLfaz2/ iq+UsmoB3fyclDGXUZmA41cq19H9DA/NF4PkS14BuuJFeMuflaI1776FAH8KX3Zpyc3o e89mB2r0tVQNU0I/GU3ZWi3cK9bxyIrUISqsveIjKKvYLxwdtRGkDXoMtHk4m8sfRY9T 60exnUuGSGDWoea4B/j871DcwKvGaNpbHlE5lmvh11Zf/MwYUnTQW7gbOM2e4iUBPwD5 e85w== Received: by 10.217.3.1 with SMTP id q1mr1863283wes.38.1346966588226; Thu, 06 Sep 2012 14:23:08 -0700 (PDT) Received: from wespe.ffwll.local (178-83-130-250.dynamic.hispeed.ch. [178.83.130.250]) by mx.google.com with ESMTPS id l5sm8618787wix.5.2012.09.06.14.23.06 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 06 Sep 2012 14:23:07 -0700 (PDT) From: Daniel Vetter To: Intel Graphics Development Date: Thu, 6 Sep 2012 22:15:41 +0200 Message-Id: <1346962544-7439-3-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.7.11.2 In-Reply-To: <1346962544-7439-1-git-send-email-daniel.vetter@ffwll.ch> References: <1346962544-7439-1-git-send-email-daniel.vetter@ffwll.ch> X-Gm-Message-State: ALoCoQm45G00ZcHwXLcAX6FHYfEiYo2BzZjJLztEI8+WJHRhsHeVq0JKgwLJ/jrzvoldOg/XgCgW Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH 2/5] drm/i915: clean up the cpu edp pll special case X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org By using the new pre_enabel/post_disable functions. To ensure that we only frob the cpu edp pll while the pipe is off add the relevant asserts. Thanks to the new output state staging, this is now really easy. Signed-Off-by: Daniel Vetter Reviewed-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_dp.c | 74 +++++++++++++++-------------------------- 1 file changed, 27 insertions(+), 47 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index c59710d..c72d4f3 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -808,9 +808,6 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, } } -static void ironlake_edp_pll_on(struct drm_encoder *encoder); -static void ironlake_edp_pll_off(struct drm_encoder *encoder); - static void intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode) @@ -821,14 +818,6 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, struct drm_crtc *crtc = intel_dp->base.base.crtc; struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - /* Turn on the eDP PLL if needed */ - if (is_edp(intel_dp)) { - if (!is_pch_edp(intel_dp)) - ironlake_edp_pll_on(encoder); - else - ironlake_edp_pll_off(encoder); - } - /* * There are four kinds of DP registers: * @@ -1191,12 +1180,16 @@ static void ironlake_edp_backlight_off(struct intel_dp *intel_dp) msleep(intel_dp->backlight_off_delay); } -static void ironlake_edp_pll_on(struct drm_encoder *encoder) +static void ironlake_edp_pll_on(struct intel_dp *intel_dp) { - struct drm_device *dev = encoder->dev; + struct drm_device *dev = intel_dp->base.base.dev; + struct drm_crtc *crtc = intel_dp->base.base.crtc; struct drm_i915_private *dev_priv = dev->dev_private; u32 dpa_ctl; + assert_pipe_disabled(dev_priv, + to_intel_crtc(crtc)->pipe); + DRM_DEBUG_KMS("\n"); dpa_ctl = I915_READ(DP_A); dpa_ctl |= DP_PLL_ENABLE; @@ -1205,12 +1198,16 @@ static void ironlake_edp_pll_on(struct drm_encoder *encoder) udelay(200); } -static void ironlake_edp_pll_off(struct drm_encoder *encoder) +static void ironlake_edp_pll_off(struct intel_dp *intel_dp) { - struct drm_device *dev = encoder->dev; + struct drm_device *dev = intel_dp->base.base.dev; + struct drm_crtc *crtc = intel_dp->base.base.crtc; struct drm_i915_private *dev_priv = dev->dev_private; u32 dpa_ctl; + assert_pipe_disabled(dev_priv, + to_intel_crtc(crtc)->pipe); + dpa_ctl = I915_READ(DP_A); dpa_ctl &= ~DP_PLL_ENABLE; I915_WRITE(DP_A, dpa_ctl); @@ -1309,6 +1306,14 @@ static void intel_disable_dp(struct intel_encoder *encoder) intel_dp_link_down(intel_dp); } +static void intel_post_disable_dp(struct intel_encoder *encoder) +{ + struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); + + if (is_cpu_edp(intel_dp)) + ironlake_edp_pll_off(intel_dp); +} + static void intel_enable_dp(struct intel_encoder *encoder) { struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); @@ -1328,39 +1333,12 @@ static void intel_enable_dp(struct intel_encoder *encoder) ironlake_edp_backlight_on(intel_dp); } -static void -intel_dp_dpms(struct drm_connector *connector, int mode) +static void intel_pre_enable_dp(struct intel_encoder *encoder) { - struct intel_dp *intel_dp = intel_attached_dp(connector); - - /* DP supports only 2 dpms states. */ - if (mode != DRM_MODE_DPMS_ON) - mode = DRM_MODE_DPMS_OFF; - - if (mode == connector->dpms) - return; - - connector->dpms = mode; - - /* Only need to change hw state when actually enabled */ - if (!intel_dp->base.base.crtc) { - intel_dp->base.connectors_active = false; - return; - } - - if (mode != DRM_MODE_DPMS_ON) { - intel_encoder_dpms(&intel_dp->base, mode); - - if (is_cpu_edp(intel_dp)) - ironlake_edp_pll_off(&intel_dp->base.base); - } else { - if (is_cpu_edp(intel_dp)) - ironlake_edp_pll_on(&intel_dp->base.base); - - intel_encoder_dpms(&intel_dp->base, mode); - } + struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); - intel_modeset_check_state(connector->dev); + if (is_cpu_edp(intel_dp)) + ironlake_edp_pll_on(intel_dp); } /* @@ -2391,7 +2369,7 @@ static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = { }; static const struct drm_connector_funcs intel_dp_connector_funcs = { - .dpms = intel_dp_dpms, + .dpms = intel_connector_dpms, .detect = intel_dp_detect, .fill_modes = drm_helper_probe_single_connector_modes, .set_property = intel_dp_set_property, @@ -2522,7 +2500,9 @@ intel_dp_init(struct drm_device *dev, int output_reg, enum port port) drm_sysfs_connector_add(connector); intel_encoder->enable = intel_enable_dp; + intel_encoder->pre_enable = intel_pre_enable_dp; intel_encoder->disable = intel_disable_dp; + intel_encoder->post_disable = intel_post_disable_dp; intel_encoder->get_hw_state = intel_dp_get_hw_state; intel_connector->get_hw_state = intel_connector_get_hw_state;