From patchwork Thu Sep 6 20:15:42 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 1417981 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork2.kernel.org (Postfix) with ESMTP id 70CBDDFFCF for ; Thu, 6 Sep 2012 21:25:41 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6C918A0D9B for ; Thu, 6 Sep 2012 14:25:41 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wi0-f177.google.com (mail-wi0-f177.google.com [209.85.212.177]) by gabe.freedesktop.org (Postfix) with ESMTP id 9ADB8A0D53 for ; Thu, 6 Sep 2012 14:23:10 -0700 (PDT) Received: by wibhn17 with SMTP id hn17so1551068wib.12 for ; Thu, 06 Sep 2012 14:23:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=AAV5zwimJ5ns9NYkYu9pKIkPvNPyj3e1LIys65Z3iwc=; b=fvmdpz5WqGNVkgxKu9NkJp486nSQJG2VnvaTG8Ps0cFmCbACb53hHzIbniGjZVaXBT 29BgYGIOKpE+BXEbQcFH1mpbApufyMsOi43LK+i/gYyKKzfcM/Efs6cYO4sfWyNSeZyn uERwIcHbjbRX3fSZXkHd41VhqVISv6froPqts= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=AAV5zwimJ5ns9NYkYu9pKIkPvNPyj3e1LIys65Z3iwc=; b=V5fgJP8F3qrmoZKHB6a0BiUWsEdebfEIu+ltvo4qQ9mjd3vxd00l5npvkRav9sTBZi dnkCjpXPNUDpOR0Nx43TY7Sl0eyb/GapPhWDRy/l39T9BpK9860bGXcrl/brtncAFAab tDW1cg6IC77urJyvqJujGsPzvJikZTqZ1Wc7cZ6yKInvjXiBWbxmveB1HRxVuGfel6SW i2b8FErnok9QU2Vl04Qy106CuZvblD0S+tWytex2vz6AzjyO0GAfGSGRItV85E4i5inY 2LZl/aSLYXxAcbllQGX5nvbOVluab8eni4UPCYBRJssw/F7e9C2YJXaAuc15dE+PX5B5 5P+w== Received: by 10.180.96.199 with SMTP id du7mr7428773wib.21.1346966589746; Thu, 06 Sep 2012 14:23:09 -0700 (PDT) Received: from wespe.ffwll.local (178-83-130-250.dynamic.hispeed.ch. [178.83.130.250]) by mx.google.com with ESMTPS id l5sm8618787wix.5.2012.09.06.14.23.08 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 06 Sep 2012 14:23:08 -0700 (PDT) From: Daniel Vetter To: Intel Graphics Development Date: Thu, 6 Sep 2012 22:15:42 +0200 Message-Id: <1346962544-7439-4-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.7.11.2 In-Reply-To: <1346962544-7439-1-git-send-email-daniel.vetter@ffwll.ch> References: <1346962544-7439-1-git-send-email-daniel.vetter@ffwll.ch> X-Gm-Message-State: ALoCoQkLPVmmo6Mr6teOBEeXmpybXw9Hc1MGENJWEH9diX3B6iuM6ScDYHfbBu189/hV2/IC4Fa3 Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH 3/5] drm/i915: robustify edp_pll_on/off X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org With the previous patch to clean up where exactly these two functions are getting called, this patch can tackle the enable/disable code itself: - WARN if the port enable bit is in the wrong state or if the edp pll bit is in the wrong state, just for paranoia's sake. - Don't disable the edp pll harder in the modeset functions just for fun. - Don't set the edp pll enable flag in intel_dp->DP in modeset, do that while changing the actual hw state. We do the same with the actual port enable bit, so this is a bit more consistent. - Track the current DP register value when setting things up and add some comments how intel_dp->DP is used in the disable code. v2: Be more careful with resetting intel_dp->DP - otherwise dpms off->on will fail spectacularly, becuase we enable the eDP port when we should only enable the eDP pll. Signed-Off-by: Daniel Vetter Reviewed-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_dp.c | 29 ++++++++++++++++++----------- 1 file changed, 18 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index c72d4f3..7c746d1 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -887,7 +887,6 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, intel_dp->DP |= intel_crtc->pipe << 29; /* don't miss out required setting for eDP */ - intel_dp->DP |= DP_PLL_ENABLE; if (adjusted_mode->clock < 200000) intel_dp->DP |= DP_PLL_FREQ_160MHZ; else @@ -909,7 +908,6 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, if (is_cpu_edp(intel_dp)) { /* don't miss out required setting for eDP */ - intel_dp->DP |= DP_PLL_ENABLE; if (adjusted_mode->clock < 200000) intel_dp->DP |= DP_PLL_FREQ_160MHZ; else @@ -1192,8 +1190,15 @@ static void ironlake_edp_pll_on(struct intel_dp *intel_dp) DRM_DEBUG_KMS("\n"); dpa_ctl = I915_READ(DP_A); - dpa_ctl |= DP_PLL_ENABLE; - I915_WRITE(DP_A, dpa_ctl); + WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n"); + WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n"); + + /* We don't adjust intel_dp->DP while tearing down the link, to + * facilitate link retraining (e.g. after hotplug). Hence clear all + * enable bits here to ensure that we don't enable too much. */ + intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE); + intel_dp->DP |= DP_PLL_ENABLE; + I915_WRITE(DP_A, intel_dp->DP); POSTING_READ(DP_A); udelay(200); } @@ -1209,6 +1214,13 @@ static void ironlake_edp_pll_off(struct intel_dp *intel_dp) to_intel_crtc(crtc)->pipe); dpa_ctl = I915_READ(DP_A); + WARN((dpa_ctl & DP_PLL_ENABLE) == 0, + "dp pll off, should be on\n"); + WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n"); + + /* We can't rely on the value tracked for the DP register in + * intel_dp->DP because link_down must not change that (otherwise link + * re-training will fail. */ dpa_ctl &= ~DP_PLL_ENABLE; I915_WRITE(DP_A, dpa_ctl); POSTING_READ(DP_A); @@ -1906,13 +1918,6 @@ intel_dp_link_down(struct intel_dp *intel_dp) DRM_DEBUG_KMS("\n"); - if (is_edp(intel_dp)) { - DP &= ~DP_PLL_ENABLE; - I915_WRITE(intel_dp->output_reg, DP); - POSTING_READ(intel_dp->output_reg); - udelay(100); - } - if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) { DP &= ~DP_LINK_TRAIN_MASK_CPT; I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT); @@ -2456,6 +2461,8 @@ intel_dp_init(struct drm_device *dev, int output_reg, enum port port) intel_dp->output_reg = output_reg; intel_dp->port = port; + /* Preserve the current hw state. */ + intel_dp->DP = I915_READ(intel_dp->output_reg); intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); if (!intel_connector) {