From patchwork Wed Sep 12 13:06:32 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paulo Zanoni X-Patchwork-Id: 1443901 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id 373994025E for ; Wed, 12 Sep 2012 13:10:11 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2ACB79EB36 for ; Wed, 12 Sep 2012 06:10:11 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-gh0-f177.google.com (mail-gh0-f177.google.com [209.85.160.177]) by gabe.freedesktop.org (Postfix) with ESMTP id 0B52B9E7E7 for ; Wed, 12 Sep 2012 06:07:27 -0700 (PDT) Received: by mail-gh0-f177.google.com with SMTP id f20so377113ghb.36 for ; Wed, 12 Sep 2012 06:07:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=E+bz3jBrHuOhVBnXJHfQfR+qCYSR3CSAKzrwzmWzIqc=; b=VA8upYPx9+jWf7sDuFbn3JruSGZmtQ/4IqeBDOM7wdT5hhlORhp2XsgMYbH/AGTanh z+io1H7xE0aeu9j0Bv/eaK7KSDOoHo/BFMXFgQA3n++zFCA16vbQHhPWTYNu2Zh+tUH2 gxIBTvO3NgW8rwxOO1dKypgJuya1Yl21bQV3gsR0rERrQHYOSk2evfXt0qJxnwjp9mVa ZVHOXfaMCEpNjNZH2Nzw9GH+4hte79Ss2gMvvSOHG3ifq/vLQjvyITjVbfaw0bgeAfDF UBESX2086zxdvpNjIdhTKmQOlz2jWgyuNhOLdrVcbOjnB7UjlSCtNbXcXXcgjdIn543g vTIA== Received: by 10.236.79.97 with SMTP id h61mr19379816yhe.16.1347455247836; Wed, 12 Sep 2012 06:07:27 -0700 (PDT) Received: from localhost.localdomain (200.188.217.18.dedicated.neoviatelecom.com.br. [200.188.217.18]) by mx.google.com with ESMTPS id p21sm35824518yhj.11.2012.09.12.06.07.26 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 12 Sep 2012 06:07:27 -0700 (PDT) From: Paulo Zanoni To: intel-gfx@lists.freedesktop.org Date: Wed, 12 Sep 2012 10:06:32 -0300 Message-Id: <1347455196-5167-5-git-send-email-przanoni@gmail.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1347455196-5167-1-git-send-email-przanoni@gmail.com> References: <1347455196-5167-1-git-send-email-przanoni@gmail.com> Cc: Paulo Zanoni Subject: [Intel-gfx] [PATCH 4/8] drm/i915: simplify setting DSPCNTR inside ironlake_crtc_mode_set X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org From: Paulo Zanoni Because declaring a variable in the beginning of the function, then initializing it 100 lines later, then using it 100 lines later does not make our code look good IMHO. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_display.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 5a4e363..b657416 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -4748,7 +4748,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc, int plane = intel_crtc->plane; int refclk, num_connectors = 0; intel_clock_t clock, reduced_clock; - u32 dpll, fp = 0, fp2 = 0, dspcntr; + u32 dpll, fp = 0, fp2 = 0; bool ok, has_reduced_clock = false, is_sdvo = false; bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false; struct intel_encoder *encoder, *edp_encoder = NULL; @@ -4950,9 +4950,6 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc, else dpll |= PLL_REF_INPUT_DREFCLK; - /* Set up the display plane register */ - dspcntr = DISPPLANE_GAMMA_ENABLE; - DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe); drm_mode_debug_printmodeline(mode); @@ -5029,7 +5026,8 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc, intel_wait_for_vblank(dev, pipe); - I915_WRITE(DSPCNTR(plane), dspcntr); + /* Set up the display plane register */ + I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE); POSTING_READ(DSPCNTR(plane)); ret = intel_pipe_set_base(crtc, x, y, fb);