| Message ID | 1347534809-13341-1-git-send-email-daniel.vetter@ffwll.ch (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
On Thu, 13 Sep 2012 13:13:29 +0200, Daniel Vetter <daniel.vetter@ffwll.ch> wrote: > While reading docs I've noticed that this special workaround to select > the 1.6 GHz DP clock only applies to pre-production ilk machines. > Since the registers we're touching here are rather undocumented and > might be harmful on later chips, rip it out. > > For the Bspec reference of this w/a look in "vol4g CPU Display > Registers [DevILK]", Section 4.1.7.1 "DP_A—DisplayPort A > Control Register", "DP_PLL_Frequency_Select". > > Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> The spec definitely says DevILK-A, are we sure it got excised in production machines? Once a w/a is implemented by the Windows driver they have a tendency to linger... So can you instead replace the w/a with a message to remind us about the possibilty of failure of the PLL to change frequencies. -Chris
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 376ae28..e2794ca 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -818,27 +818,11 @@ static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock) dpa_ctl = I915_READ(DP_A); dpa_ctl &= ~DP_PLL_FREQ_MASK; - if (clock < 200000) { - u32 temp; + if (clock < 200000) dpa_ctl |= DP_PLL_FREQ_160MHZ; - /* workaround for 160Mhz: - 1) program 0x4600c bits 15:0 = 0x8124 - 2) program 0x46010 bit 0 = 1 - 3) program 0x46034 bit 24 = 1 - 4) program 0x64000 bit 14 = 1 - */ - temp = I915_READ(0x4600c); - temp &= 0xffff0000; - I915_WRITE(0x4600c, temp | 0x8124); - - temp = I915_READ(0x46010); - I915_WRITE(0x46010, temp | 1); - - temp = I915_READ(0x46034); - I915_WRITE(0x46034, temp | (1 << 24)); - } else { + else dpa_ctl |= DP_PLL_FREQ_270MHZ; - } + I915_WRITE(DP_A, dpa_ctl); POSTING_READ(DP_A);
While reading docs I've noticed that this special workaround to select the 1.6 GHz DP clock only applies to pre-production ilk machines. Since the registers we're touching here are rather undocumented and might be harmful on later chips, rip it out. For the Bspec reference of this w/a look in "vol4g CPU Display Registers [DevILK]", Section 4.1.7.1 "DP_A—DisplayPort A Control Register", "DP_PLL_Frequency_Select". Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> --- drivers/gpu/drm/i915/intel_dp.c | 22 +++------------------- 1 file changed, 3 insertions(+), 19 deletions(-)