From patchwork Thu Sep 13 11:13:29 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 1452031 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id EBB503FE79 for ; Thu, 13 Sep 2012 12:21:56 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A9811A0E2B for ; Thu, 13 Sep 2012 05:21:56 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wi0-f177.google.com (mail-wi0-f177.google.com [209.85.212.177]) by gabe.freedesktop.org (Postfix) with ESMTP id 03484A0E5D for ; Thu, 13 Sep 2012 05:21:02 -0700 (PDT) Received: by wibhn17 with SMTP id hn17so2736424wib.12 for ; Thu, 13 Sep 2012 05:21:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=from:to:cc:subject:date:message-id:x-mailer:mime-version :content-type:content-transfer-encoding; bh=Sq11/2F0g8lR947MxLnnSQ68DhGg6G63JBcfZq7B5DE=; b=KwYG0rfStGKGVPfqBpKLqSO7vz/H7/keBzQ3yAZISDKVC5xydAtjKCHXIztyVsVme/ QFfbcZ+nDMF0bE60Q9PYmbf8h2GktedFOq996JbUdSAXXOvG4PDKCb34vn1UDvDXaGOP JtKKTtB+ExuWw7e11pS6hMGMca3mtqnSkPR1A= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:mime-version :content-type:content-transfer-encoding:x-gm-message-state; bh=Sq11/2F0g8lR947MxLnnSQ68DhGg6G63JBcfZq7B5DE=; b=hjEPXQzFuydGQh2A0JOy7y9aQ//w5aBI3Zc8W8egxTAaKCMknRp3binGyoYUsvcDpJ X64EwyDXq8o7IOiu+UNtYRVyDWJ2wohsiTGJiB5+MuGCdG9y0V7j58kaxUXotkzuCGb0 aJPzcnEc6MeCUxwTihnVy3Wo05dkq8MZjQUJuFoGA0jr6lp35U4A5QUzRK3ZJa7I0lNv 4tys3rCgsNucWEQ5aK3L/olkMF8uTBMPWw7ls1gOgwhUb0vkpzh08UZzvHeMnz7VCJ9I Io4iE4SeceDiaRU8MUdZ0sxwydK4TUVS06P4q9dEWOSZSy3x9pjQ7ytkhTG7/7ng4WOm i6kg== Received: by 10.180.102.136 with SMTP id fo8mr4493057wib.19.1347538862247; Thu, 13 Sep 2012 05:21:02 -0700 (PDT) Received: from wespe.ffwll.local (178-83-130-250.dynamic.hispeed.ch. [178.83.130.250]) by mx.google.com with ESMTPS id t7sm20087224wix.6.2012.09.13.05.21.00 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 13 Sep 2012 05:21:01 -0700 (PDT) From: Daniel Vetter To: Intel Graphics Development Date: Thu, 13 Sep 2012 13:13:29 +0200 Message-Id: <1347534809-13341-1-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.7.11.2 MIME-Version: 1.0 X-Gm-Message-State: ALoCoQkA384QbVvj8d+imY78ewBxuCNMdYG/SgrERe0kqmHv6ZN89tk2iSZ+Ai8TEbYcltY+oLyh Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH] drm/i915: rip out pre-production ilk cpu edp w/a X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org While reading docs I've noticed that this special workaround to select the 1.6 GHz DP clock only applies to pre-production ilk machines. Since the registers we're touching here are rather undocumented and might be harmful on later chips, rip it out. For the Bspec reference of this w/a look in "vol4g CPU Display Registers [DevILK]", Section 4.1.7.1 "DP_A—DisplayPort A Control Register", "DP_PLL_Frequency_Select". Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_dp.c | 22 +++------------------- 1 file changed, 3 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 376ae28..e2794ca 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -818,27 +818,11 @@ static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock) dpa_ctl = I915_READ(DP_A); dpa_ctl &= ~DP_PLL_FREQ_MASK; - if (clock < 200000) { - u32 temp; + if (clock < 200000) dpa_ctl |= DP_PLL_FREQ_160MHZ; - /* workaround for 160Mhz: - 1) program 0x4600c bits 15:0 = 0x8124 - 2) program 0x46010 bit 0 = 1 - 3) program 0x46034 bit 24 = 1 - 4) program 0x64000 bit 14 = 1 - */ - temp = I915_READ(0x4600c); - temp &= 0xffff0000; - I915_WRITE(0x4600c, temp | 0x8124); - - temp = I915_READ(0x46010); - I915_WRITE(0x46010, temp | 1); - - temp = I915_READ(0x46034); - I915_WRITE(0x46034, temp | (1 << 24)); - } else { + else dpa_ctl |= DP_PLL_FREQ_270MHZ; - } + I915_WRITE(DP_A, dpa_ctl); POSTING_READ(DP_A);