From patchwork Tue Sep 18 00:10:15 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Widawsky X-Patchwork-Id: 1470071 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id B5CDE3FCFC for ; Tue, 18 Sep 2012 00:10:39 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5F8659F5D3 for ; Mon, 17 Sep 2012 17:10:39 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from shiva.chad-versace.us (209-20-75-48.static.cloud-ips.com [209.20.75.48]) by gabe.freedesktop.org (Postfix) with ESMTP id B5E529EF4F for ; Mon, 17 Sep 2012 17:10:25 -0700 (PDT) Received: by shiva.chad-versace.us (Postfix, from userid 1005) id 534D0885C0; Tue, 18 Sep 2012 00:11:08 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.2 (2011-06-06) on shiva.chad-versace.us X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED autolearn=unavailable version=3.3.2 Received: from lundgren.jf.intel.com (unknown [134.134.139.76]) by shiva.chad-versace.us (Postfix) with ESMTPSA id 5E759885A4; Tue, 18 Sep 2012 00:11:01 +0000 (UTC) From: Ben Widawsky To: intel-gfx@lists.freedesktop.org Date: Mon, 17 Sep 2012 17:10:15 -0700 Message-Id: <1347927015-15553-1-git-send-email-ben@bwidawsk.net> X-Mailer: git-send-email 1.7.12 Cc: Ben Widawsky Subject: [Intel-gfx] [PATCH] drm/i915: Valleyview doesn't have rc6+ or rc6++ X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org I do not currently have a VLV to test this on, but hopefully it only removes information from debugfs, sysfs, and prevents enabling an unsupported mode. CC: Jesse Barnes Signed-off-by: Ben Widawsky Reviewed-by: Rodrigo Vivi --- drivers/gpu/drm/i915/i915_debugfs.c | 5 +++++ drivers/gpu/drm/i915/i915_sysfs.c | 3 +++ drivers/gpu/drm/i915/intel_pm.c | 4 ++-- 3 files changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 7a4b3f3..4e74a6a 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -1144,11 +1144,16 @@ static int gen6_drpc_info(struct seq_file *m) I915_READ(GEN6_GT_GFX_RC6_LOCKED)); seq_printf(m, "RC6 residency since boot: %u\n", I915_READ(GEN6_GT_GFX_RC6)); + + if (IS_VALLEYVIEW(dev)) + goto out; + seq_printf(m, "RC6+ residency since boot: %u\n", I915_READ(GEN6_GT_GFX_RC6p)); seq_printf(m, "RC6++ residency since boot: %u\n", I915_READ(GEN6_GT_GFX_RC6pp)); +out: return 0; } diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c index a253515..4717a42 100644 --- a/drivers/gpu/drm/i915/i915_sysfs.c +++ b/drivers/gpu/drm/i915/i915_sysfs.c @@ -41,6 +41,9 @@ static u32 calc_residency(struct drm_device *dev, const u32 reg) if (!intel_enable_rc6(dev)) return 0; + if (IS_VALLEYVIEW(dev) && reg != GEN6_GT_GFX_RC6) + return 0; + raw_time = I915_READ(reg) * 128ULL; return DIV_ROUND_UP_ULL(raw_time, 100000); } diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 82ca172..ccd50d7 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -2389,8 +2389,8 @@ int intel_enable_rc6(const struct drm_device *dev) } /* snb/ivb have more than one rc6 state. */ - if (INTEL_INFO(dev)->gen == 6) { - DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n"); + if (INTEL_INFO(dev)->gen == 6 || IS_VALLEYVIEW(dev)) { + DRM_DEBUG_DRIVER("HW doesn't support deep RC6 (disabling)\n"); return INTEL_RC6_ENABLE; }