| Message ID | 1348493576-3386-2-git-send-email-przanoni@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
I know almost nothing about hdmi infoframes, but isn't hdmi infoframes limited to 30 bytes + 1 checksum byte? (From HDMI Spec 8.2 section) On Mon, Sep 24, 2012 at 10:32 AM, Paulo Zanoni <przanoni@gmail.com> wrote: > From: Paulo Zanoni <paulo.r.zanoni@intel.com> > > If we don't write at least 32 DIP bytes the InfoFrame ECC may not be > correctly calculated in some cases (e.g., when changing the port), and > this will lead to black screens on HDMI monitors. The ECC value is > generated by the hardware. > > I don't see how this should break anything since we're writing 0 and > that should be the correct value, so this patch should be safe. > > This patch fixes bug #46761, which is marked as a regression > introduced by commit 4e89ee174bb2da341bf90a84321c7008a3c9210d: > drm/i915: set the DIP port on ibx_write_infoframe > > Before commit 4e89 we were just failing to send AVI infoframes when we > needed to change the port, which can lead to black screens in some > cases. After commit 4e89 we started sending infoframes, but with a > possibly wrong ECC value. After this patch I hope we start sending > correct infoframes. > > Cc: stable@vger.kernel.org > Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=46761 > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> > --- > drivers/gpu/drm/i915/intel_hdmi.c | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c > index f9fb47c..4ca355e 100644 > --- a/drivers/gpu/drm/i915/intel_hdmi.c > +++ b/drivers/gpu/drm/i915/intel_hdmi.c > @@ -151,6 +151,8 @@ static void g4x_write_infoframe(struct drm_encoder *encoder, > I915_WRITE(VIDEO_DIP_DATA, *data); > data++; > } > + for (; i < 32; i += 4) > + I915_WRITE(VIDEO_DIP_DATA, 0); > mmiowb(); > > val |= g4x_infoframe_enable(frame); > @@ -186,6 +188,8 @@ static void ibx_write_infoframe(struct drm_encoder *encoder, > I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); > data++; > } > + for (; i < 32; i += 4) > + I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); > mmiowb(); > > val |= g4x_infoframe_enable(frame); > @@ -224,6 +228,8 @@ static void cpt_write_infoframe(struct drm_encoder *encoder, > I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); > data++; > } > + for (; i < 32; i += 4) > + I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); > mmiowb(); > > val |= g4x_infoframe_enable(frame); > @@ -259,6 +265,8 @@ static void vlv_write_infoframe(struct drm_encoder *encoder, > I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); > data++; > } > + for (; i < 32; i += 4) > + I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0); > mmiowb(); > > val |= g4x_infoframe_enable(frame); > @@ -292,6 +300,8 @@ static void hsw_write_infoframe(struct drm_encoder *encoder, > I915_WRITE(data_reg + i, *data); > data++; > } > + for (; i < 32; i += 4) > + I915_WRITE(data_reg + i, 0); > mmiowb(); > > val |= hsw_infoframe_enable(frame); > -- > 1.7.10.4 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index f9fb47c..4ca355e 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -151,6 +151,8 @@ static void g4x_write_infoframe(struct drm_encoder *encoder, I915_WRITE(VIDEO_DIP_DATA, *data); data++; } + for (; i < 32; i += 4) + I915_WRITE(VIDEO_DIP_DATA, 0); mmiowb(); val |= g4x_infoframe_enable(frame); @@ -186,6 +188,8 @@ static void ibx_write_infoframe(struct drm_encoder *encoder, I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); data++; } + for (; i < 32; i += 4) + I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); mmiowb(); val |= g4x_infoframe_enable(frame); @@ -224,6 +228,8 @@ static void cpt_write_infoframe(struct drm_encoder *encoder, I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); data++; } + for (; i < 32; i += 4) + I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); mmiowb(); val |= g4x_infoframe_enable(frame); @@ -259,6 +265,8 @@ static void vlv_write_infoframe(struct drm_encoder *encoder, I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); data++; } + for (; i < 32; i += 4) + I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0); mmiowb(); val |= g4x_infoframe_enable(frame); @@ -292,6 +300,8 @@ static void hsw_write_infoframe(struct drm_encoder *encoder, I915_WRITE(data_reg + i, *data); data++; } + for (; i < 32; i += 4) + I915_WRITE(data_reg + i, 0); mmiowb(); val |= hsw_infoframe_enable(frame);