From patchwork Tue Oct 2 20:51:47 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paulo Zanoni X-Patchwork-Id: 1538821 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork2.kernel.org (Postfix) with ESMTP id A5749DFFAD for ; Tue, 2 Oct 2012 20:59:19 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B16AE9F36F for ; Tue, 2 Oct 2012 13:59:19 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-gh0-f177.google.com (mail-gh0-f177.google.com [209.85.160.177]) by gabe.freedesktop.org (Postfix) with ESMTP id 94FF79EEA7 for ; Tue, 2 Oct 2012 13:53:17 -0700 (PDT) Received: by mail-gh0-f177.google.com with SMTP id f20so1791743ghb.36 for ; Tue, 02 Oct 2012 13:53:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=K6Y/ufS5ZKJohRVHMQio0LeNOLi+lafqnOh3npNYdmA=; b=i+zdezLy+pAtJVAAwCzungf5hR7+hIZbQ+gBD9Kc+NdiJA1WPbuTZzaNOe4pE2G7Q/ HY1XYWAU92D5mRLm8PNLQZHdDmS7VqDuEdJUdfbXU473o6rsxJeUgKP7CpA4bdnyblL2 GOk+XlShGWobTuT9yOBzgLuC8JGD9/Wd05wQXaauvGuy0lk2gIuR7ObcxWYOdlXh62cP tAHSuoEBZzmYNP7nC6hOjRw/JC8X/kXrOpuAIo5CRB6/J7/K75/kwELtEc84BypY0Dmo FCDl0qpll1HFWWySmwHjQ2sbcxZxZnvRDweBCptjlndMTtB/CAOUf/Zd+PcTwOETSj2o ToCg== Received: by 10.101.166.35 with SMTP id t35mr6127052ano.63.1349211197258; Tue, 02 Oct 2012 13:53:17 -0700 (PDT) Received: from vicky.domain.invalid ([187.59.149.118]) by mx.google.com with ESMTPS id f1sm2117168ank.12.2012.10.02.13.53.15 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 02 Oct 2012 13:53:16 -0700 (PDT) From: Paulo Zanoni To: intel-gfx@lists.freedesktop.org Date: Tue, 2 Oct 2012 17:51:47 -0300 Message-Id: <1349211142-4802-13-git-send-email-przanoni@gmail.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1349211142-4802-1-git-send-email-przanoni@gmail.com> References: <1349211142-4802-1-git-send-email-przanoni@gmail.com> Cc: Paulo Zanoni Subject: [Intel-gfx] [PATCH 12/47] drm/i915: add intel_ddi_set_pipe_settings X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org From: Paulo Zanoni In theory, all the DDI pipe settings should be set here, including timing and M/N registers. For now, let's just set the DP MSA attributes. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/i915_reg.h | 10 ++++++++++ drivers/gpu/drm/i915/intel_ddi.c | 33 +++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_display.c | 4 +++- drivers/gpu/drm/i915/intel_drv.h | 1 + 4 files changed, 47 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index ec58a23..9318121 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4526,6 +4526,16 @@ #define PIPE_CLK_SEL_DISABLED (0x0<<29) #define PIPE_CLK_SEL_PORT(x) ((x+1)<<29) +#define _PIPEA_MSA_MISC 0x60410 +#define _PIPEB_MSA_MISC 0x61410 +#define PIPE_MSA_MISC(pipe) _PIPE(pipe, _PIPEA_MSA_MISC, _PIPEB_MSA_MISC) +#define PIPE_MSA_SYNC_CLK (1<<0) +#define PIPE_MSA_6_BPC (0<<5) +#define PIPE_MSA_8_BPC (1<<5) +#define PIPE_MSA_10_BPC (2<<5) +#define PIPE_MSA_12_BPC (3<<5) +#define PIPE_MSA_16_BPC (3<<5) + /* LCPLL Control */ #define LCPLL_CTL 0x130040 #define LCPLL_PLL_DISABLE (1<<31) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index cf1bb99..fc6679c 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -827,6 +827,39 @@ bool intel_ddi_pll_mode_set(struct drm_crtc *crtc, int clock) return true; } +void intel_ddi_set_pipe_settings(struct drm_crtc *crtc) +{ + struct drm_i915_private *dev_priv = crtc->dev->dev_private; + struct intel_crtc *intel_crtc = to_intel_crtc(crtc); + struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); + enum pipe pipe = intel_crtc->pipe; + int type = intel_encoder->type; + uint32_t temp; + + if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { + + temp = PIPE_MSA_SYNC_CLK; + switch (intel_crtc->bpp) { + case 18: + temp |= PIPE_MSA_6_BPC; + break; + case 24: + temp |= PIPE_MSA_8_BPC; + break; + case 30: + temp |= PIPE_MSA_10_BPC; + break; + case 36: + temp |= PIPE_MSA_12_BPC; + break; + default: + WARN(1, "%d bpp unsupported by pipe DDI function\n", + intel_crtc->bpp); + } + I915_WRITE(PIPE_MSA_MISC(pipe), temp); + } +} + void intel_ddi_enable_pipe_func(struct drm_crtc *crtc) { struct intel_crtc *intel_crtc = to_intel_crtc(crtc); diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 5080b53..7f0016a 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -3218,8 +3218,10 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc) */ intel_crtc_load_lut(crtc); - if (IS_HASWELL(dev)) + if (IS_HASWELL(dev)) { + intel_ddi_set_pipe_settings(crtc); intel_ddi_enable_pipe_func(crtc); + } intel_enable_pipe(dev_priv, pipe, is_pch_port); intel_enable_plane(dev_priv, plane, pipe); diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 7e1e670..ed75a36 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -597,5 +597,6 @@ extern bool intel_ddi_pll_mode_set(struct drm_crtc *crtc, int clock); extern void intel_ddi_pre_enable(struct intel_encoder *intel_encoder); extern void intel_ddi_post_disable(struct intel_encoder *intel_encoder); extern void intel_ddi_put_crtc_pll(struct drm_crtc *crtc); +extern void intel_ddi_set_pipe_settings(struct drm_crtc *crtc); #endif /* __INTEL_DRV_H__ */