From patchwork Tue Oct 2 20:51:36 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paulo Zanoni X-Patchwork-Id: 1538711 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id A57193FDAE for ; Tue, 2 Oct 2012 20:54:07 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5D93B9E74C for ; Tue, 2 Oct 2012 13:54:07 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-gh0-f177.google.com (mail-gh0-f177.google.com [209.85.160.177]) by gabe.freedesktop.org (Postfix) with ESMTP id B57219F0E9 for ; Tue, 2 Oct 2012 13:52:58 -0700 (PDT) Received: by ghbf20 with SMTP id f20so1791743ghb.36 for ; Tue, 02 Oct 2012 13:52:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=WIL293ivmJa/imiOOr7yeJgooI3etLsmmFCc/YWD6Iw=; b=FGeQjSD/6wIvKh//CSHBP79bHVuWs/WjeN3bc8W4XXHtO2dVFd5HL3WZCFucBnWXps 5sPBiHQGVjs/048bnSCzm+P7w8vcCWej9EaR5ZWpbR3wIMjy17f9bMUOdwica5W5LrGK p4HN5xC6BVlonpZAPozKMNKcjck9ADslb+vCf9grkXngz3cp2zGY6p1x/rcGByQzR+Fh 1USTdfKlDT28NMjv1lnCiO4gmH4Gn2XwwNnjzXTCCRdw6+jXSpmMKVUmSW2lJ90czTXJ 07+cWqfKc1cmeuQ/p0Ci95Ds/QseIS04X8QeCLT8zXGUeu37teplV57aswqClqy3rH5G nHew== Received: by 10.101.46.17 with SMTP id y17mr1774947anj.19.1349211178049; Tue, 02 Oct 2012 13:52:58 -0700 (PDT) Received: from vicky.domain.invalid ([187.59.149.118]) by mx.google.com with ESMTPS id f1sm2117168ank.12.2012.10.02.13.52.55 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 02 Oct 2012 13:52:56 -0700 (PDT) From: Paulo Zanoni To: intel-gfx@lists.freedesktop.org Date: Tue, 2 Oct 2012 17:51:36 -0300 Message-Id: <1349211142-4802-2-git-send-email-przanoni@gmail.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1349211142-4802-1-git-send-email-przanoni@gmail.com> References: <1349211142-4802-1-git-send-email-przanoni@gmail.com> Cc: Paulo Zanoni Subject: [Intel-gfx] [PATCH 01/47] drm/i915: rewrite the LCPLL code X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org From: Paulo Zanoni Right now, we're trying to enable LCPLL at every mode set, but we're never disabling it. Also, we really don't want to be disabling LCPLL since it requires a very complex disable sequence. So instead of enabling it at every mode set, enable it once. Also, we are currently not checking if the desired values are the ones we're actually reading/writing, so add some code to check the values and give us warning messages. Since the disable/enable sequence is very complex, I am not sure that the single I915_WRITE we have is enough, but keep it for now to avoid regressions since everybody's machines seem to be working. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/i915_reg.h | 7 ++++++ drivers/gpu/drm/i915/intel_ddi.c | 46 +++++++++++++++++++++++++++++----- drivers/gpu/drm/i915/intel_display.c | 7 ++++++ drivers/gpu/drm/i915/intel_drv.h | 1 + 4 files changed, 55 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index d17bef7..ab96706 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4527,8 +4527,15 @@ #define LCPLL_CTL 0x130040 #define LCPLL_PLL_DISABLE (1<<31) #define LCPLL_PLL_LOCK (1<<30) +#define LCPLL_CLK_FREQ_MASK (3<<26) +#define LCPLL_CLK_FREQ_450 (0<<26) +#define LCPLL_CLK_FREQ_540 (1<<26) #define LCPLL_CD_CLOCK_DISABLE (1<<25) #define LCPLL_CD2X_CLOCK_DISABLE (1<<23) +#define LCPLL_CD_SOURCE_FCLK (1<<21) + +#define CDCLK_FREQ 0x46200 +#define CDCLK_FREQ_MASK 0x3FF /* Pipe WM_LINETIME - watermark line time */ #define PIPE_WM_LINETIME_A 0x45270 diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index bfe3754..34a73a1 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -682,12 +682,6 @@ void intel_ddi_mode_set(struct drm_encoder *encoder, DRM_DEBUG_KMS("WR PLL: %dKHz refresh rate with p=%d, n2=%d r2=%d\n", crtc->mode.clock, p, n2, r2); - /* Enable LCPLL if disabled */ - temp = I915_READ(LCPLL_CTL); - if (temp & LCPLL_PLL_DISABLE) - I915_WRITE(LCPLL_CTL, - temp & ~LCPLL_PLL_DISABLE); - /* Configure WR PLL 1, program the correct divider values for * the desired frequency and wait for warmup */ I915_WRITE(WRPLL_CTL1, @@ -817,3 +811,43 @@ void intel_disable_ddi(struct intel_encoder *encoder) I915_WRITE(DDI_BUF_CTL(port), temp); } + +void intel_ddi_pll_init(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + uint32_t lcpll_val, clk_val, temp; + bool lcpll_needs_change = false; + + /* Check the LCPLL state and fix it if needed. */ + lcpll_val = I915_READ(LCPLL_CTL); + clk_val = I915_READ(CDCLK_FREQ) & CDCLK_FREQ_MASK; + DRM_DEBUG_KMS("CDCLK running at %dMHz\n", clk_val + 1); + + temp = lcpll_val & LCPLL_CLK_FREQ_MASK; + if ((clk_val == 449 && (temp != LCPLL_CLK_FREQ_450)) || + (clk_val == 539 && (temp != LCPLL_CLK_FREQ_540))) { + DRM_ERROR("LCPLL and CDCLK frequencies don't match\n"); + lcpll_needs_change = true; + + lcpll_val &= ~LCPLL_CLK_FREQ_MASK; + if (clk_val == 449) + lcpll_val |= LCPLL_CLK_FREQ_450; + else + lcpll_val |= LCPLL_CLK_FREQ_540; + } + + if (lcpll_val & LCPLL_CD_SOURCE_FCLK) { + DRM_ERROR("CDCLK source is not LCPLL\n"); + lcpll_needs_change = true; + lcpll_val &= ~LCPLL_CD_SOURCE_FCLK; + } + + if (lcpll_val & LCPLL_PLL_DISABLE) { + DRM_ERROR("LCPLL is disabled\n"); + lcpll_needs_change = true; + lcpll_val &= ~LCPLL_PLL_DISABLE; + } + + if (lcpll_needs_change) + I915_WRITE(LCPLL_CTL, lcpll_val); +} diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 6cf0d00..40f98d1 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -7477,6 +7477,12 @@ static const struct drm_crtc_funcs intel_crtc_funcs = { .page_flip = intel_crtc_page_flip, }; +static void intel_cpu_pll_init(struct drm_device *dev) +{ + if (IS_HASWELL(dev)) + intel_ddi_pll_init(dev); +} + static void intel_pch_pll_init(struct drm_device *dev) { drm_i915_private_t *dev_priv = dev->dev_private; @@ -8085,6 +8091,7 @@ void intel_modeset_init(struct drm_device *dev) DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret); } + intel_cpu_pll_init(dev); intel_pch_pll_init(dev); /* Just disable it once at startup */ diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 79f8ed6..57566b7 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -580,5 +580,6 @@ extern bool intel_ddi_get_hw_state(struct intel_encoder *encoder, extern void intel_ddi_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode); +extern void intel_ddi_pll_init(struct drm_device *dev); #endif /* __INTEL_DRV_H__ */