From patchwork Tue Oct 2 20:52:05 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paulo Zanoni X-Patchwork-Id: 1539011 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork2.kernel.org (Postfix) with ESMTP id 6F862DFFAD for ; Tue, 2 Oct 2012 21:07:48 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 77E169E7CF for ; Tue, 2 Oct 2012 14:07:48 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-yx0-f177.google.com (mail-yx0-f177.google.com [209.85.213.177]) by gabe.freedesktop.org (Postfix) with ESMTP id 343559E74C for ; Tue, 2 Oct 2012 13:53:48 -0700 (PDT) Received: by mail-yx0-f177.google.com with SMTP id r1so1792077yen.36 for ; Tue, 02 Oct 2012 13:53:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=mxieASk1ONqImmT7jbjumgYI1cku+aaFVgu6pUwY2bw=; b=hv1Zql5zoU10X7f59JpHunOpc9297oRYLX9PZWLZxvfiSrDd2hnGy+d6VAOzYJkGfE waWj7F/yhUaUgSnjJLGklmB2Hu+cdLzhWpCk+Odc6PsOMNOA/geV+gO0cC7ibUW37EnE QCv3pR0mbOIFwf5YmIgy1XX8q3M83Y19wI6ojHMW2Uwqk8EaCVPZESLMCXnKiBDehwx2 suqWt11IZtJG6HgFoa7LPg8AQFZ+zcVYpQtnLGLLgPM064rjvFbVVM64OqFqOhRNVvF2 TD7jDURaodvMtP9/yanA4RgTOdAV/CvEMwZZmD4RM6TvAM3xsAo7QfVcORoi0NpMcLE7 aTLg== Received: by 10.236.127.83 with SMTP id c59mr1824066yhi.123.1349211227873; Tue, 02 Oct 2012 13:53:47 -0700 (PDT) Received: from vicky.domain.invalid ([187.59.149.118]) by mx.google.com with ESMTPS id f1sm2117168ank.12.2012.10.02.13.53.46 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 02 Oct 2012 13:53:47 -0700 (PDT) From: Paulo Zanoni To: intel-gfx@lists.freedesktop.org Date: Tue, 2 Oct 2012 17:52:05 -0300 Message-Id: <1349211142-4802-31-git-send-email-przanoni@gmail.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1349211142-4802-1-git-send-email-przanoni@gmail.com> References: <1349211142-4802-1-git-send-email-przanoni@gmail.com> Cc: Paulo Zanoni Subject: [Intel-gfx] [PATCH 30/47] drm/i915: convert PIPE_MSA_MISC to transcoder X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org From: Paulo Zanoni Same as the other registers. This one also appeared on Haswell for the first time, so that's why we are renaming it. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/i915_reg.h | 19 ++++++++++--------- drivers/gpu/drm/i915/intel_ddi.c | 16 ++++++++-------- 2 files changed, 18 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 127e33f..b21d31c 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4544,15 +4544,16 @@ #define TRANS_CLK_SEL_DISABLED (0x0<<29) #define TRANS_CLK_SEL_PORT(x) ((x+1)<<29) -#define _PIPEA_MSA_MISC 0x60410 -#define _PIPEB_MSA_MISC 0x61410 -#define PIPE_MSA_MISC(pipe) _PIPE(pipe, _PIPEA_MSA_MISC, _PIPEB_MSA_MISC) -#define PIPE_MSA_SYNC_CLK (1<<0) -#define PIPE_MSA_6_BPC (0<<5) -#define PIPE_MSA_8_BPC (1<<5) -#define PIPE_MSA_10_BPC (2<<5) -#define PIPE_MSA_12_BPC (3<<5) -#define PIPE_MSA_16_BPC (3<<5) +#define _TRANSA_MSA_MISC 0x60410 +#define _TRANSB_MSA_MISC 0x61410 +#define TRANS_MSA_MISC(tran) _TRANSCODER(tran, _TRANSA_MSA_MISC, \ + _TRANSB_MSA_MISC) +#define TRANS_MSA_SYNC_CLK (1<<0) +#define TRANS_MSA_6_BPC (0<<5) +#define TRANS_MSA_8_BPC (1<<5) +#define TRANS_MSA_10_BPC (2<<5) +#define TRANS_MSA_12_BPC (3<<5) +#define TRANS_MSA_16_BPC (3<<5) /* LCPLL Control */ #define LCPLL_CTL 0x130040 diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 26aae8f..980a591 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -888,31 +888,31 @@ void intel_ddi_set_pipe_settings(struct drm_crtc *crtc) struct drm_i915_private *dev_priv = crtc->dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(crtc); struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); - enum pipe pipe = intel_crtc->pipe; + enum transcoder transcoder = intel_crtc->transcoder; int type = intel_encoder->type; uint32_t temp; if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { - temp = PIPE_MSA_SYNC_CLK; + temp = TRANS_MSA_SYNC_CLK; switch (intel_crtc->bpp) { case 18: - temp |= PIPE_MSA_6_BPC; + temp |= TRANS_MSA_6_BPC; break; case 24: - temp |= PIPE_MSA_8_BPC; + temp |= TRANS_MSA_8_BPC; break; case 30: - temp |= PIPE_MSA_10_BPC; + temp |= TRANS_MSA_10_BPC; break; case 36: - temp |= PIPE_MSA_12_BPC; + temp |= TRANS_MSA_12_BPC; break; default: - WARN(1, "%d bpp unsupported by pipe DDI function\n", + WARN(1, "%d bpp unsupported by DDI function\n", intel_crtc->bpp); } - I915_WRITE(PIPE_MSA_MISC(pipe), temp); + I915_WRITE(TRANS_MSA_MISC(transcoder), temp); } }