From patchwork Tue Oct 2 20:52:07 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paulo Zanoni X-Patchwork-Id: 1539031 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id E714C3FDAE for ; Tue, 2 Oct 2012 21:08:40 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id ED5CC9E81F for ; Tue, 2 Oct 2012 14:08:40 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-gh0-f177.google.com (mail-gh0-f177.google.com [209.85.160.177]) by gabe.freedesktop.org (Postfix) with ESMTP id 052029EF60 for ; Tue, 2 Oct 2012 13:53:51 -0700 (PDT) Received: by mail-gh0-f177.google.com with SMTP id f20so1791743ghb.36 for ; Tue, 02 Oct 2012 13:53:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=QEdZqVefOs1dKgyOfbR4MX6agiMSvwVRih98yVlSulw=; b=DMrme+oHZ7abpFqxDJgh173F32qGBGZgNuj8dxiD6FjKnn6AP3ACmns3Iy7FlrA7+a VrFs25L0/MpStk3hutv8eofhsxme7/leF/jSFLMBymcnLYNKhDZJ0ONDzI5eQqvhO9qk 2PWIf/e8ruBXHmJMjjEzpCIRHLz/ArfuyyWfgcz4VNNivAq3q81i6T/CToenjgTXWEpa iyPe5zma5+2XQ2E6rziPu+zQzgEzg7ZSxuh/GWLmkogm9X78FtEDTPqmVPnv2Atf+i4g itxUw3s5Yd4mMzr3MEWoiG1RKNQm/+BLVahfPjd14iplGw9AwTty4dcxDVp6y0KXIPgP Sgzg== Received: by 10.236.92.235 with SMTP id j71mr19430040yhf.128.1349211231603; Tue, 02 Oct 2012 13:53:51 -0700 (PDT) Received: from vicky.domain.invalid ([187.59.149.118]) by mx.google.com with ESMTPS id f1sm2117168ank.12.2012.10.02.13.53.49 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 02 Oct 2012 13:53:51 -0700 (PDT) From: Paulo Zanoni To: intel-gfx@lists.freedesktop.org Date: Tue, 2 Oct 2012 17:52:07 -0300 Message-Id: <1349211142-4802-33-git-send-email-przanoni@gmail.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1349211142-4802-1-git-send-email-przanoni@gmail.com> References: <1349211142-4802-1-git-send-email-przanoni@gmail.com> Cc: Paulo Zanoni Subject: [Intel-gfx] [PATCH 32/47] drm/i915: convert pipe timing definitions to transcoder X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org From: Paulo Zanoni Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/i915_irq.c | 7 +++-- drivers/gpu/drm/i915/i915_reg.h | 14 +++++----- drivers/gpu/drm/i915/intel_crt.c | 6 ++-- drivers/gpu/drm/i915/intel_display.c | 51 +++++++++++++++++----------------- 4 files changed, 40 insertions(+), 38 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 024b08d..09b3551 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -185,6 +185,7 @@ static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe, int vbl_start, vbl_end, htotal, vtotal; bool in_vbl = true; int ret = 0; + enum transcoder transcoder = pipe_to_transcoder(dev_priv, pipe); if (!i915_pipe_enabled(dev, pipe)) { DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled " @@ -193,7 +194,7 @@ static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe, } /* Get vtotal. */ - vtotal = 1 + ((I915_READ(VTOTAL(pipe)) >> 16) & 0x1fff); + vtotal = 1 + ((I915_READ(VTOTAL(transcoder)) >> 16) & 0x1fff); if (INTEL_INFO(dev)->gen >= 4) { /* No obvious pixelcount register. Only query vertical @@ -213,13 +214,13 @@ static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe, */ position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT; - htotal = 1 + ((I915_READ(HTOTAL(pipe)) >> 16) & 0x1fff); + htotal = 1 + ((I915_READ(HTOTAL(transcoder)) >> 16) & 0x1fff); *vpos = position / htotal; *hpos = position - (*vpos * htotal); } /* Query vblank area. */ - vbl = I915_READ(VBLANK(pipe)); + vbl = I915_READ(VBLANK(transcoder)); /* Test position against vblank region. */ vbl_start = vbl & 0x1fff; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 4715754..3b91031 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1561,14 +1561,14 @@ #define _VSYNCSHIFT_B 0x61028 -#define HTOTAL(pipe) _PIPE(pipe, _HTOTAL_A, _HTOTAL_B) -#define HBLANK(pipe) _PIPE(pipe, _HBLANK_A, _HBLANK_B) -#define HSYNC(pipe) _PIPE(pipe, _HSYNC_A, _HSYNC_B) -#define VTOTAL(pipe) _PIPE(pipe, _VTOTAL_A, _VTOTAL_B) -#define VBLANK(pipe) _PIPE(pipe, _VBLANK_A, _VBLANK_B) -#define VSYNC(pipe) _PIPE(pipe, _VSYNC_A, _VSYNC_B) +#define HTOTAL(trans) _TRANSCODER(trans, _HTOTAL_A, _HTOTAL_B) +#define HBLANK(trans) _TRANSCODER(trans, _HBLANK_A, _HBLANK_B) +#define HSYNC(trans) _TRANSCODER(trans, _HSYNC_A, _HSYNC_B) +#define VTOTAL(trans) _TRANSCODER(trans, _VTOTAL_A, _VTOTAL_B) +#define VBLANK(trans) _TRANSCODER(trans, _VBLANK_A, _VBLANK_B) +#define VSYNC(trans) _TRANSCODER(trans, _VSYNC_A, _VSYNC_B) #define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B) -#define VSYNCSHIFT(pipe) _PIPE(pipe, _VSYNCSHIFT_A, _VSYNCSHIFT_B) +#define VSYNCSHIFT(trans) _TRANSCODER(trans, _VSYNCSHIFT_A, _VSYNCSHIFT_B) /* VGA port control */ #define ADPA 0x61100 diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c index bc2a91f..4f32ea9 100644 --- a/drivers/gpu/drm/i915/intel_crt.c +++ b/drivers/gpu/drm/i915/intel_crt.c @@ -484,9 +484,9 @@ intel_crt_load_detect(struct intel_crt *crt) DRM_DEBUG_KMS("starting load-detect on CRT\n"); bclrpat_reg = BCLRPAT(pipe); - vtotal_reg = VTOTAL(pipe); - vblank_reg = VBLANK(pipe); - vsync_reg = VSYNC(pipe); + vtotal_reg = VTOTAL(transcoder); + vblank_reg = VBLANK(transcoder); + vsync_reg = VSYNC(transcoder); pipeconf_reg = PIPECONF(transcoder); pipe_dsl_reg = PIPEDSL(pipe); diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index aa5cc84..15b2a4f 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -3019,14 +3019,14 @@ static void ironlake_pch_enable(struct drm_crtc *crtc) /* set transcoder timing, panel must allow it */ assert_panel_unlocked(dev_priv, pipe); - I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe))); - I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe))); - I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe))); + I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(transcoder))); + I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(transcoder))); + I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(transcoder))); - I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe))); - I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe))); - I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe))); - I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe))); + I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(transcoder))); + I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(transcoder))); + I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(transcoder))); + I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(transcoder))); if (!IS_HASWELL(dev)) intel_fdi_normal_train(crtc); @@ -4338,6 +4338,7 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc, struct drm_device *dev = intel_crtc->base.dev; struct drm_i915_private *dev_priv = dev->dev_private; enum pipe pipe = intel_crtc->pipe; + enum transcoder transcoder = intel_crtc->transcoder; uint32_t vsyncshift; if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { @@ -4351,25 +4352,25 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc, } if (INTEL_INFO(dev)->gen > 3) - I915_WRITE(VSYNCSHIFT(pipe), vsyncshift); + I915_WRITE(VSYNCSHIFT(transcoder), vsyncshift); - I915_WRITE(HTOTAL(pipe), + I915_WRITE(HTOTAL(transcoder), (adjusted_mode->crtc_hdisplay - 1) | ((adjusted_mode->crtc_htotal - 1) << 16)); - I915_WRITE(HBLANK(pipe), + I915_WRITE(HBLANK(transcoder), (adjusted_mode->crtc_hblank_start - 1) | ((adjusted_mode->crtc_hblank_end - 1) << 16)); - I915_WRITE(HSYNC(pipe), + I915_WRITE(HSYNC(transcoder), (adjusted_mode->crtc_hsync_start - 1) | ((adjusted_mode->crtc_hsync_end - 1) << 16)); - I915_WRITE(VTOTAL(pipe), + I915_WRITE(VTOTAL(transcoder), (adjusted_mode->crtc_vdisplay - 1) | ((adjusted_mode->crtc_vtotal - 1) << 16)); - I915_WRITE(VBLANK(pipe), + I915_WRITE(VBLANK(transcoder), (adjusted_mode->crtc_vblank_start - 1) | ((adjusted_mode->crtc_vblank_end - 1) << 16)); - I915_WRITE(VSYNC(pipe), + I915_WRITE(VSYNC(transcoder), (adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) << 16)); @@ -6333,12 +6334,12 @@ struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, { struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - int pipe = intel_crtc->pipe; + enum transcoder transcoder = intel_crtc->transcoder; struct drm_display_mode *mode; - int htot = I915_READ(HTOTAL(pipe)); - int hsync = I915_READ(HSYNC(pipe)); - int vtot = I915_READ(VTOTAL(pipe)); - int vsync = I915_READ(VSYNC(pipe)); + int htot = I915_READ(HTOTAL(transcoder)); + int hsync = I915_READ(HSYNC(transcoder)); + int vtot = I915_READ(VTOTAL(transcoder)); + int vsync = I915_READ(VSYNC(transcoder)); mode = kzalloc(sizeof(*mode), GFP_KERNEL); if (!mode) @@ -8807,12 +8808,12 @@ intel_display_capture_error_state(struct drm_device *dev) error->pipe[i].conf = I915_READ(PIPECONF(transcoder)); error->pipe[i].source = I915_READ(PIPESRC(i)); - error->pipe[i].htotal = I915_READ(HTOTAL(i)); - error->pipe[i].hblank = I915_READ(HBLANK(i)); - error->pipe[i].hsync = I915_READ(HSYNC(i)); - error->pipe[i].vtotal = I915_READ(VTOTAL(i)); - error->pipe[i].vblank = I915_READ(VBLANK(i)); - error->pipe[i].vsync = I915_READ(VSYNC(i)); + error->pipe[i].htotal = I915_READ(HTOTAL(transcoder)); + error->pipe[i].hblank = I915_READ(HBLANK(transcoder)); + error->pipe[i].hsync = I915_READ(HSYNC(transcoder)); + error->pipe[i].vtotal = I915_READ(VTOTAL(transcoder)); + error->pipe[i].vblank = I915_READ(VBLANK(transcoder)); + error->pipe[i].vsync = I915_READ(VSYNC(transcoder)); } return error;