diff mbox

[10/10] drm/i915: pipe and planes should be disabled on haswell_crtc_mode_set

Message ID 1349449561-3599-11-git-send-email-przanoni@gmail.com (mailing list archive)
State New, archived
Headers show

Commit Message

Paulo Zanoni Oct. 5, 2012, 3:06 p.m. UTC 
From: Paulo Zanoni <paulo.r.zanoni@intel.com>

So WARN in case they're not. It also does not make any sense to
wait_for_vblank at this point.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

Comments

Lespiau, Damien Oct. 10, 2012, 9:57 p.m. UTC | #1 
On Fri, Oct 5, 2012 at 4:06 PM, Paulo Zanoni <przanoni@gmail.com> wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> So WARN in case they're not. It also does not make any sense to
> wait_for_vblank at this point.
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Daniel Vetter Oct. 10, 2012, 10:47 p.m. UTC | #2 
On Wed, Oct 10, 2012 at 10:57:05PM +0100, Lespiau, Damien wrote:
> On Fri, Oct 5, 2012 at 4:06 PM, Paulo Zanoni <przanoni@gmail.com> wrote:
> > From: Paulo Zanoni <paulo.r.zanoni@intel.com>
> >
> > So WARN in case they're not. It also does not make any sense to
> > wait_for_vblank at this point.
> >
> > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> 
> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>

Last two patches are now also merged, thanks.
-Daniel
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 709497d..705ed80 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5217,6 +5217,11 @@  static int haswell_crtc_mode_set(struct drm_crtc *crtc,
 	WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
 	     num_connectors, pipe_name(pipe));
 
+	WARN_ON(I915_READ(PIPECONF(pipe)) &
+		(PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
+
+	WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
+
 	if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
 		return -EINVAL;
 
@@ -5357,8 +5362,6 @@  static int haswell_crtc_mode_set(struct drm_crtc *crtc,
 
 	haswell_set_pipeconf(crtc, adjusted_mode, dither);
 
-	intel_wait_for_vblank(dev, pipe);
-
 	/* Set up the display plane register */
 	I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
 	POSTING_READ(DSPCNTR(plane));