From patchwork Thu Oct 18 21:21:32 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paulo Zanoni X-Patchwork-Id: 1613631 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork2.kernel.org (Postfix) with ESMTP id CADD3E018D for ; Thu, 18 Oct 2012 21:23:41 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C37CD9EAEE for ; Thu, 18 Oct 2012 14:23:41 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-gh0-f177.google.com (mail-gh0-f177.google.com [209.85.160.177]) by gabe.freedesktop.org (Postfix) with ESMTP id 6D45EA0A0D for ; Thu, 18 Oct 2012 14:22:07 -0700 (PDT) Received: by mail-gh0-f177.google.com with SMTP id f20so2458142ghb.36 for ; Thu, 18 Oct 2012 14:22:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=aLpAUdOjzq0+aYbLi9BQediUXh1jfdY/BzhHXls2PmA=; b=LqoPnEBq7utpq/G39qhxo8gbovNpNug4pb3R325gUPxVdURSO8eMEQ2c0Q+n5xDt1l GXW6ZbZISmDd6QwjyIT0v2mIgQNyI8wa/1lRZqgCD+gBOnEtxleLv9DdwzBTQtgb1ES5 aCk31CPe2VlIYZFiWxqNxvJBMgyR/Z6MWh1CU0t3Od6FMROczKZuv5qpslgf62tAHEBg 8s26Ne5fA9KirnPrZOiA8tGnll1miA+lXDB5anvR588TNTmeOy8ryQSv6DXVDhiivWVw PJFrtNv7nTKOQllik2ve8vdHiNx29y0v7RNLhZJPP2gVAz2TitlZ+owoD2LQT+8gzl7K SPmQ== Received: by 10.236.124.131 with SMTP id x3mr22033286yhh.14.1350595326797; Thu, 18 Oct 2012 14:22:06 -0700 (PDT) Received: from vicky.domain.invalid ([177.16.81.162]) by mx.google.com with ESMTPS id o13sm22450078ang.1.2012.10.18.14.22.05 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 18 Oct 2012 14:22:06 -0700 (PDT) From: Paulo Zanoni To: intel-gfx@lists.freedesktop.org Date: Thu, 18 Oct 2012 18:21:32 -0300 Message-Id: <1350595304-18237-3-git-send-email-przanoni@gmail.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1350595304-18237-1-git-send-email-przanoni@gmail.com> References: <1350595304-18237-1-git-send-email-przanoni@gmail.com> Cc: Paulo Zanoni Subject: [Intel-gfx] [PATCH 02/14] drm/i915: convert PIPE_CLK_SEL to transcoder X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org From: Paulo Zanoni This register appeared in Haswell. It does not have an EDP version because the EDP transcoder is always tied to the DDIA clock. Notice that if we call PIPE_CLK_SEL(pipe) when pipe is PIPE_A and transcoder is TRANSCODER_EDP we might introduce a bug, that's why this is a transcoder register even though it does not have an EDP version. Even though Haswell names this register PIPE_CLK_SEL, it will be renamed to TRANS_CLK_SEL in the future, so let's just start using the real name that makes more sense and avoids misusage. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/i915_reg.h | 14 +++++++------- drivers/gpu/drm/i915/intel_ddi.c | 10 ++++++++-- 2 files changed, 15 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index c3fd536..32cad88 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4539,13 +4539,13 @@ #define PORT_CLK_SEL_WRPLL2 (5<<29) #define PORT_CLK_SEL_NONE (7<<29) -/* Pipe clock selection */ -#define PIPE_CLK_SEL_A 0x46140 -#define PIPE_CLK_SEL_B 0x46144 -#define PIPE_CLK_SEL(pipe) _PIPE(pipe, PIPE_CLK_SEL_A, PIPE_CLK_SEL_B) -/* For each pipe, we need to select the corresponding port clock */ -#define PIPE_CLK_SEL_DISABLED (0x0<<29) -#define PIPE_CLK_SEL_PORT(x) ((x+1)<<29) +/* Transcoder clock selection */ +#define TRANS_CLK_SEL_A 0x46140 +#define TRANS_CLK_SEL_B 0x46144 +#define TRANS_CLK_SEL(tran) _TRANSCODER(tran, TRANS_CLK_SEL_A, TRANS_CLK_SEL_B) +/* For each transcoder, we need to select the corresponding port clock */ +#define TRANS_CLK_SEL_DISABLED (0x0<<29) +#define TRANS_CLK_SEL_PORT(x) ((x+1)<<29) #define _PIPEA_MSA_MISC 0x60410 #define _PIPEB_MSA_MISC 0x61410 diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 81cca48..f568862 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -1095,15 +1095,21 @@ void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc) struct drm_i915_private *dev_priv = crtc->dev->dev_private; struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); enum port port = intel_ddi_get_encoder_port(intel_encoder); + enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder; - I915_WRITE(PIPE_CLK_SEL(intel_crtc->pipe), PIPE_CLK_SEL_PORT(port)); + if (cpu_transcoder != TRANSCODER_EDP) + I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), + TRANS_CLK_SEL_PORT(port)); } void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc) { struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; + enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder; - I915_WRITE(PIPE_CLK_SEL(intel_crtc->pipe), PIPE_CLK_SEL_DISABLED); + if (cpu_transcoder != TRANSCODER_EDP) + I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), + TRANS_CLK_SEL_DISABLED); } void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)