From patchwork Sat Oct 20 18:57:43 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 1621961 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork2.kernel.org (Postfix) with ESMTP id D8687DF26F for ; Sat, 20 Oct 2012 18:59:46 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C6D149EB48 for ; Sat, 20 Oct 2012 11:59:46 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wi0-f177.google.com (mail-wi0-f177.google.com [209.85.212.177]) by gabe.freedesktop.org (Postfix) with ESMTP id 9C80E9E8E2 for ; Sat, 20 Oct 2012 11:57:54 -0700 (PDT) Received: by mail-wi0-f177.google.com with SMTP id hj13so983567wib.12 for ; Sat, 20 Oct 2012 11:57:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=i+EyNq52/S4yex3lTndMlBGzu4uitnxJuS06Yi7odMs=; b=F0knWsx1DLEEaKrZV3wSjcZADrDt9wC1WhYPO02lHF02Jx6YyqzX+o+KYWAOVpwKtz 0s/G//OnafogOMiH4jZPx2dzxogMQT40goexG9n81kRMenyNac+waOyDutn/5wxn+Z8n 3udGse1b4OQnkOuLS7SEvXXaBzfsYyX7VWdTs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=i+EyNq52/S4yex3lTndMlBGzu4uitnxJuS06Yi7odMs=; b=d2p0QUth+wO43qB7yjazlGJuz/P0OSqADQ0J+ONTCNHDHoBsFr6P/1zMWq0FgsxbyF y9wY5Cj2x+aljriCQoeR3ycYwuFV3ObDdoXjApDwsshhZb2oXM/lm7VjWMETSIsgSR6p kHkBE6dt4ZtdqnEeDfe8QMOSySwiGqr0DKRowJMJjlmTXIWlkxBwtk5K283vegGuHqDH WDfie8wwgpL8BPsSCSlOFwJoUNkUke0CoEwQN55btSXa26+LrERbyR5AWN4lBE26NA/K E02NBekbLsVA1jnCdIZ4OhWPok49bCh/xifZRHIghJRXrONOe/Vp90fjutXCk/l5n4QU /7bQ== Received: by 10.180.97.35 with SMTP id dx3mr10798283wib.14.1350759473642; Sat, 20 Oct 2012 11:57:53 -0700 (PDT) Received: from bremse.ffwll.local (178-83-130-250.dynamic.hispeed.ch. [178.83.130.250]) by mx.google.com with ESMTPS id fp6sm21608299wib.0.2012.10.20.11.57.52 (version=TLSv1/SSLv3 cipher=OTHER); Sat, 20 Oct 2012 11:57:53 -0700 (PDT) From: Daniel Vetter To: Intel Graphics Development Date: Sat, 20 Oct 2012 20:57:43 +0200 Message-Id: <1350759465-7171-4-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.7.11.4 In-Reply-To: <1350759465-7171-1-git-send-email-daniel.vetter@ffwll.ch> References: <1350759465-7171-1-git-send-email-daniel.vetter@ffwll.ch> X-Gm-Message-State: ALoCoQmMdxFeFvxcrOSbivKqs3SgM6BjhMJxUBmUgvChX2B7hK7B5aTsNqZ0mFBi5XuV/cfKRZJ5 Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH 3/5] drm/i915/eDP: compute the panel power clock divisor from the pch rawclock X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org We need this when the bios forgets even to set that bit up. Most seem to do that, even when they don't set up anything else in the panel power sequencer. Note that on IBX the rawclk is variable according to Bspec, but everyone is using 125MHz. The rawclk is fixed to 125MHz on CPT, but luckily we still have the same register available. On hsw, different variants have different clocks, hence we need to check the register. Since other pieces are driven by the rawclock, too, keep the little helper in a central place. Signed-off-by: Daniel Vetter Reviewed-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_display.c | 10 ++++++++++ drivers/gpu/drm/i915/intel_dp.c | 8 ++++++-- drivers/gpu/drm/i915/intel_drv.h | 2 ++ 3 files changed, 18 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 9c17a0a7..7fb032f 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -80,6 +80,16 @@ struct intel_limit { /* FDI */ #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */ +int +intel_pch_rawclk(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + + WARN_ON(!HAS_PCH_SPLIT(dev)); + + return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; +} + static bool intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, int target, int refclk, intel_clock_t *match_clock, diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 49846c0..b35d5bd 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -2749,8 +2749,12 @@ intel_dp_init(struct drm_device *dev, int output_reg, enum port port) (final.t8 << PANEL_LIGHT_ON_DELAY_SHIFT); pp_off = (final.t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) | (final.t10 << PANEL_POWER_DOWN_DELAY_SHIFT); - pp_div = (pp_div & PP_REFERENCE_DIVIDER_MASK) | - (DIV_ROUND_UP(final.t11_t12, 1000) << PANEL_POWER_CYCLE_DELAY_SHIFT); + /* Compute the divisor for the pp clock, simply match the Bspec + * formula. */ + pp_div = ((100 * intel_pch_rawclk(dev))/2 - 1) + << PP_REFERENCE_DIVIDER_SHIFT; + pp_div |= (DIV_ROUND_UP(final.t11_t12, 1000) + << PANEL_POWER_CYCLE_DELAY_SHIFT); /* Haswell doesn't have any port selection bits for the panel * power sequence any more. */ diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index ed75a36..39bddd7 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -396,6 +396,8 @@ struct intel_fbc_work { int interval; }; +int intel_pch_rawclk(struct drm_device *dev); + int intel_connector_update_modes(struct drm_connector *connector, struct edid *edid); int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);