From patchwork Mon Oct 22 10:44:18 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 1625201 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id E7E443FC1A for ; Mon, 22 Oct 2012 10:44:37 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A19009E852 for ; Mon, 22 Oct 2012 03:44:37 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-ee0-f49.google.com (mail-ee0-f49.google.com [74.125.83.49]) by gabe.freedesktop.org (Postfix) with ESMTP id 4D1919E79D for ; Mon, 22 Oct 2012 03:44:27 -0700 (PDT) Received: by mail-ee0-f49.google.com with SMTP id c1so938966eek.36 for ; Mon, 22 Oct 2012 03:44:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=from:to:cc:subject:date:message-id:x-mailer:mime-version :content-type:content-transfer-encoding; bh=piWCQANwyDwgjaNs/2HnaZWeG8239GoMbvBDoq8u9I8=; b=ebEHuyic7FIqpI0izl/yMkkBmKLK7/nqzIAhx4n3eap0XTu42InmqnYGj3hrwQAZgZ Eihi0DzmdDvYVu5hpmmQ8sideoNacNjsxuyj6RGnx8T/s+4u/r5eGQ9SNjN9rQFM7ONq 3NGPSu/2FCU7vKXuWo2JEh7kz0g1eB2wmZaaI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:mime-version :content-type:content-transfer-encoding:x-gm-message-state; bh=piWCQANwyDwgjaNs/2HnaZWeG8239GoMbvBDoq8u9I8=; b=Dg7ggy2spv8vY6MNaHmo/w/U/7GogUKDaAV47TFAvhPgXb1GwXWOEyYCFgorQy8Lav IndhqzxkvfpkLeGBxsEHzUIvtbZcnw2GRuLVfYfvpr0Vb5+qnvX2SdlX/RSVgcVH0WRF eFlMWCym0UYZCWev5nq7h4JgQhU6EmkuV0eQbl8hcMrs58NpMCx+7s38Kve+0J1Nk08i x6xgX9F4IJARkiYG55fJRahQY69Coswkc9MNG6PMmbLyvZA8x1rbNH5BhP8tjCQ5iXhc U1tSh8ySxZrqAUU/A67cCV8iEtB1ks5nxMrDaNQCVchRKpUXY8hu9+d0iuA18tEY7MVJ 0EUQ== Received: by 10.14.172.137 with SMTP id t9mr11570304eel.2.1350902665986; Mon, 22 Oct 2012 03:44:25 -0700 (PDT) Received: from muecke.ffwll.local (178-83-130-250.dynamic.hispeed.ch. [178.83.130.250]) by mx.google.com with ESMTPS id z43sm15353980een.16.2012.10.22.03.44.25 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 22 Oct 2012 03:44:25 -0700 (PDT) From: Daniel Vetter To: Intel Graphics Development Date: Mon, 22 Oct 2012 12:44:18 +0200 Message-Id: <1350902658-1956-1-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.7.11.4 MIME-Version: 1.0 X-Gm-Message-State: ALoCoQmLoRK0ZinhlWkaR4EvuT9+MxA7WyKQo/z77ik7v429SUm289eHh8kTIls40dco/ic4+9Cb Cc: Daniel Vetter , stable@vger.kernel.org Subject: [Intel-gfx] [PATCH] drm/i915: fix overlay on i830M X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org The overlay on the i830M has a peculiar failure mode: It works the first time around after boot-up, but consistenly hangs the second time it's used. Chris Wilson has dug out a nice errata: "1.5.12 Clock Gating Disable for Display Register Address Offset: 06200h–06203h "Bit 3 Ovrunit Clock Gating Disable. 0 = Clock gating controlled by unit enabling logic 1 = Disable clock gating function DevALM Errata ALM049: Overlay Clock Gating Must be Disabled: Overlay & L2 Cache clock gating must be disabled in order to prevent device hangs when turning off overlay.SW must turn off Ovrunit clock gating (6200h) and L2 Cache clock gating (C8h)." Now I've nowhere found that 0xc8 register and hence couldn't apply the l2 cache workaround. But I've remembered that part of the magic that the OVERLAY_ON/OFF commands are supposed to do is to rearrange cache allocations so that the overlay scaler has some scratch space. And while pondering how that could explain the hang the 2nd time we enable the overlay, I've remembered that the old ums overlay code did _not_ issue the OVERLAY_OFF cmd. And indeed, disabling the OFF cmd results in the overlay working flawlessly, so I guess we can workaround the lack of the above workaround by simply never disabling the overlay engine once it's enabled. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=47827 Cc: stable@vger.kernel.org Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_overlay.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c index 555912f..0604af2 100644 --- a/drivers/gpu/drm/i915/intel_overlay.c +++ b/drivers/gpu/drm/i915/intel_overlay.c @@ -342,9 +342,15 @@ static int intel_overlay_off(struct intel_overlay *overlay) intel_ring_emit(ring, flip_addr); intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP); /* turn overlay off */ - intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_OFF); - intel_ring_emit(ring, flip_addr); - intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP); + if (IS_I830(dev)) { + intel_ring_emit(ring, MI_NOOP); + intel_ring_emit(ring, MI_NOOP); + intel_ring_emit(ring, MI_NOOP); + } else { + intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_OFF); + intel_ring_emit(ring, flip_addr); + intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP); + } intel_ring_advance(ring); return intel_overlay_do_wait_request(overlay, intel_overlay_off_tail);