From patchwork Mon Oct 22 10:55:55 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 1625211 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork2.kernel.org (Postfix) with ESMTP id 73563DF2F5 for ; Mon, 22 Oct 2012 10:56:13 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6F4369E9B8 for ; Mon, 22 Oct 2012 03:56:13 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-ee0-f49.google.com (mail-ee0-f49.google.com [74.125.83.49]) by gabe.freedesktop.org (Postfix) with ESMTP id 930BD9E79D for ; Mon, 22 Oct 2012 03:56:02 -0700 (PDT) Received: by mail-ee0-f49.google.com with SMTP id c1so943368eek.36 for ; Mon, 22 Oct 2012 03:56:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=from:to:cc:subject:date:message-id:x-mailer:mime-version :content-type:content-transfer-encoding; bh=swg0MFKAyZqwoSqKv1x31MyusQRMtNxixNzXspTVaIs=; b=ISbxpYQ3HXzjuJ4Yr/EQttzo8B7hGiaMMl48ddHlvpuUmRmt3eX6j3jbxP+3SQbJJc csnfTufPXFR+HcKgu8YFFmNXH46yIha3DOO43GObNhJuCTUAnxQkQBQ7Xah0QXLZyO1n sDMp4yyQv2xx5sLTo4QDaSFQ54nYpn15Z9jJo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:mime-version :content-type:content-transfer-encoding:x-gm-message-state; bh=swg0MFKAyZqwoSqKv1x31MyusQRMtNxixNzXspTVaIs=; b=RnuvosZcx68ZMFGpF5AceWsqSHAESuOeD2nbO/OXE7P8fD2hhxCe7Z8pxp2nuFRxSp iYu2FcKJdZEZ8RVb3fDn+lLHdUGcZ7u9Oo8HgtVcG/jxTt4WsliSxftJZLVjRvrogIeF XK+lUceUKL6Y8n1weAHmub4cVlIiFC0ESGaoJ40551SYgpBR+wbmq4W925+PuGCK5wJp oo2IEHQVCBMHC08IA5jfr9JDlx+/5OFEDTAI1VAX/ZFtWU0HLaTecYYJpuM/uzvkX0wA 3XArg5flVlMWCZ5BPhp0e2X2C9hafiHVPT4kGDsjtg29CUwUaxgxX3k+zm7epe15WaHN lhoA== Received: by 10.14.182.5 with SMTP id n5mr11434357eem.5.1350903361455; Mon, 22 Oct 2012 03:56:01 -0700 (PDT) Received: from muecke.ffwll.local (178-83-130-250.dynamic.hispeed.ch. [178.83.130.250]) by mx.google.com with ESMTPS id z43sm15401763een.16.2012.10.22.03.56.00 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 22 Oct 2012 03:56:00 -0700 (PDT) From: Daniel Vetter To: Intel Graphics Development Date: Mon, 22 Oct 2012 12:55:55 +0200 Message-Id: <1350903355-2102-1-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.7.11.4 MIME-Version: 1.0 X-Gm-Message-State: ALoCoQlp0+cRxljWIMoXbls39Zuc7sbS/mhCsAeOF75Yi8Wz6AsLHmporMp8WfY9noMPMqXw5ySy Cc: Daniel Vetter , stable@vger.kernel.org Subject: [Intel-gfx] [PATCH] drm/i915: fix overlay on i830M X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org The overlay on the i830M has a peculiar failure mode: It works the first time around after boot-up, but consistenly hangs the second time it's used. Chris Wilson has dug out a nice errata: "1.5.12 Clock Gating Disable for Display Register Address Offset: 06200h–06203h "Bit 3 Ovrunit Clock Gating Disable. 0 = Clock gating controlled by unit enabling logic 1 = Disable clock gating function DevALM Errata ALM049: Overlay Clock Gating Must be Disabled: Overlay & L2 Cache clock gating must be disabled in order to prevent device hangs when turning off overlay.SW must turn off Ovrunit clock gating (6200h) and L2 Cache clock gating (C8h)." Now I've nowhere found that 0xc8 register and hence couldn't apply the l2 cache workaround. But I've remembered that part of the magic that the OVERLAY_ON/OFF commands are supposed to do is to rearrange cache allocations so that the overlay scaler has some scratch space. And while pondering how that could explain the hang the 2nd time we enable the overlay, I've remembered that the old ums overlay code did _not_ issue the OVERLAY_OFF cmd. And indeed, disabling the OFF cmd results in the overlay working flawlessly, so I guess we can workaround the lack of the above workaround by simply never disabling the overlay engine once it's enabled. v2: Add a comment in the code. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=47827 Cc: stable@vger.kernel.org Signed-off-by: Daniel Vetter Tested-by: Rhys Reviewed-by: Chris Wilson --- drivers/gpu/drm/i915/intel_overlay.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c index 555912f..e3b095f 100644 --- a/drivers/gpu/drm/i915/intel_overlay.c +++ b/drivers/gpu/drm/i915/intel_overlay.c @@ -342,9 +342,17 @@ static int intel_overlay_off(struct intel_overlay *overlay) intel_ring_emit(ring, flip_addr); intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP); /* turn overlay off */ - intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_OFF); - intel_ring_emit(ring, flip_addr); - intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP); + if (IS_I830(dev)) { + /* Workaround: Don't disable the overlay fully, since otherwise + * it dies on the next OVERLAY_ON cmd. */ + intel_ring_emit(ring, MI_NOOP); + intel_ring_emit(ring, MI_NOOP); + intel_ring_emit(ring, MI_NOOP); + } else { + intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_OFF); + intel_ring_emit(ring, flip_addr); + intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP); + } intel_ring_advance(ring); return intel_overlay_do_wait_request(overlay, intel_overlay_off_tail);