From patchwork Tue Oct 23 20:30:05 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paulo Zanoni X-Patchwork-Id: 1633491 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id A99893FD85 for ; Tue, 23 Oct 2012 20:38:14 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 87A329F782 for ; Tue, 23 Oct 2012 13:38:14 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-gg0-f177.google.com (mail-gg0-f177.google.com [209.85.161.177]) by gabe.freedesktop.org (Postfix) with ESMTP id B6BBB9F778 for ; Tue, 23 Oct 2012 13:30:48 -0700 (PDT) Received: by mail-gg0-f177.google.com with SMTP id h1so813111gge.36 for ; Tue, 23 Oct 2012 13:30:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=wnLnIxZRu+iT3CslSjIGNwgKroVrMDlqIfFMzcLIKfk=; b=XolQ+e79jr7GLxL1OJwLNwy7msa49gId+DdmglfMnq0CTlYHSM/X3yAA6Ooh85qAMy RXyoHuA0d1pruDOWfMU5Qx9igR46LjJRIU87DQuCNGPrz/E0H+wSPzAcPNrG1WxnAISU eopUEiR0Glt8s8CqtgGSbRjcb8fxO8mfR35psje2FDq6maIJLmZGTM9ou9hMnT+ot4P2 F4uePF4Ope/9Vky2WeIM6UliMi+qLJdCunm53paEJb/RwWccwbTPslCMDg0xKFDFD+oY 0LAyACSkOLm73x5n9D+/W+tKST3nkNlBvhXb6RN+4vL08MU1ALZjOc40Vl6XWG+h0GS6 929Q== Received: by 10.236.84.194 with SMTP id s42mr12767301yhe.17.1351024248585; Tue, 23 Oct 2012 13:30:48 -0700 (PDT) Received: from vicky.domain.invalid ([177.40.46.113]) by mx.google.com with ESMTPS id a44sm12892049yhe.21.2012.10.23.13.30.46 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 23 Oct 2012 13:30:48 -0700 (PDT) From: Paulo Zanoni To: intel-gfx@lists.freedesktop.org Date: Tue, 23 Oct 2012 18:30:05 -0200 Message-Id: <1351024208-3489-16-git-send-email-przanoni@gmail.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1351024208-3489-1-git-send-email-przanoni@gmail.com> References: <1351024208-3489-1-git-send-email-przanoni@gmail.com> Cc: Paulo Zanoni Subject: [Intel-gfx] [PATCH 15/18] drm/i915: set the correct eDP aux channel clock divider on DDI X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org From: Paulo Zanoni The cdclk frequency is not always the same, so the value here should be adjusted to match it. Version 2: call intel_ddi_get_cdclk_freq instead of reading CDCLK_FREQ, because the register is just for earlier HW steppings. Signed-off-by: Paulo Zanoni Reviewed-by: Rodrigo Vivi --- drivers/gpu/drm/i915/intel_ddi.c | 2 +- drivers/gpu/drm/i915/intel_dp.c | 4 +++- drivers/gpu/drm/i915/intel_drv.h | 1 + 3 files changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 106c375..30b0db7 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -1239,7 +1239,7 @@ void intel_disable_ddi(struct intel_encoder *encoder) /* This will be needed in the future, so leave it here for now */ } -static int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv) +int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv) { if (I915_READ(HSW_FUSE_STRAP) & HSW_CDCLK_LIMIT) return 450; diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index f15ea22..6d30b2d 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -370,7 +370,9 @@ intel_dp_aux_ch(struct intel_dp *intel_dp, * clock divider. */ if (is_cpu_edp(intel_dp)) { - if (IS_VALLEYVIEW(dev)) + if (IS_HASWELL(dev)) + aux_clock_divider = intel_ddi_get_cdclk_freq(dev_priv) >> 1; + else if (IS_VALLEYVIEW(dev)) aux_clock_divider = 100; else if (IS_GEN6(dev) || IS_GEN7(dev)) aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */ diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 65927d9..c05e892 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -609,6 +609,7 @@ extern bool intel_ddi_get_hw_state(struct intel_encoder *encoder, extern void intel_ddi_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode); +extern int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv); extern void intel_ddi_pll_init(struct drm_device *dev); extern void intel_ddi_enable_pipe_func(struct drm_crtc *crtc); extern void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,