From patchwork Tue Oct 23 20:29:52 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paulo Zanoni X-Patchwork-Id: 1633171 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id 435023FD4E for ; Tue, 23 Oct 2012 20:31:58 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 26FB19F75B for ; Tue, 23 Oct 2012 13:31:58 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-yh0-f49.google.com (mail-yh0-f49.google.com [209.85.213.49]) by gabe.freedesktop.org (Postfix) with ESMTP id 72B0E9F770 for ; Tue, 23 Oct 2012 13:30:28 -0700 (PDT) Received: by mail-yh0-f49.google.com with SMTP id j52so813033yhj.36 for ; Tue, 23 Oct 2012 13:30:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=WcLlvvTmKfaj11r6qkpuod3DdN+3UINnygyLm6RfAyc=; b=NlbZDiyHaFEnc7v7mheHFWCKVr1JkuMZIB5tBqnUOrIQy23MZ2qHB1gis0NXNSLD9w EKNsiz1FVYnDDf1nJL8rWkDzQscx4934HIz5i2W2zx9ceZ/TxL3zndz5DD7zldtRGElH 9RPcpFggY3w/it96yVseKDcq4OU8oO9FuDQWkb2HMUdWh+u4ldsYR8Zn4qPGKDxOlgsg WTBxMuvYKM0cnQ2LHwHgg4b10kuNwyE4SPRYfBQLF102cxfYa+ctdPaVvK3sgFQALfQj XkJQNUg+l3FnB+GakzWjnRFsqmDvi/R/nvrpKIDi5SHq2Xa+X69VgK7bqwtmnxHgRqNZ wNKA== Received: by 10.236.118.16 with SMTP id k16mr12693409yhh.66.1351024227978; Tue, 23 Oct 2012 13:30:27 -0700 (PDT) Received: from vicky.domain.invalid ([177.40.46.113]) by mx.google.com with ESMTPS id a44sm12892049yhe.21.2012.10.23.13.30.26 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 23 Oct 2012 13:30:27 -0700 (PDT) From: Paulo Zanoni To: intel-gfx@lists.freedesktop.org Date: Tue, 23 Oct 2012 18:29:52 -0200 Message-Id: <1351024208-3489-3-git-send-email-przanoni@gmail.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1351024208-3489-1-git-send-email-przanoni@gmail.com> References: <1351024208-3489-1-git-send-email-przanoni@gmail.com> Cc: Paulo Zanoni Subject: [Intel-gfx] [PATCH 02/18] drm/i915: fix the checks inside Ironlake/Haswell crtc enable/disable X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org From: Paulo Zanoni The last commit just forked the functions, this one removes Haswell code from the Ironlake functions and removes Ironlake code from the Haswell functions. It is worth noticing that we are not considering CPT possible on Haswell anymore. So far on Haswell enablement we kept trying to still consider IBX/CPT as a possibility with a Haswell CPU, but this was never tested, I really doubt it will work with the current code and we don't really have plans to support it. Future patches will remove the IBX/CPT code from other Haswell functions. Notice that we still have a WARN on haswell_crtc_mode_set in case we detect non-LPT PCH. Signed-off-by: Paulo Zanoni Reviewed-by: Rodrigo Vivi --- drivers/gpu/drm/i915/intel_display.c | 73 ++++-------------------------------- 1 file changed, 7 insertions(+), 66 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index eb4dba6..a90da35 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -3228,9 +3228,6 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc) if (encoder->pre_enable) encoder->pre_enable(encoder); - if (IS_HASWELL(dev)) - intel_ddi_enable_pipe_clock(intel_crtc); - /* Enable panel fitting for LVDS */ if (dev_priv->pch_pf_size && (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) { @@ -3249,11 +3246,6 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc) */ intel_crtc_load_lut(crtc); - if (IS_HASWELL(dev)) { - intel_ddi_set_pipe_settings(crtc); - intel_ddi_enable_pipe_func(crtc); - } - intel_enable_pipe(dev_priv, pipe, is_pch_port); intel_enable_plane(dev_priv, plane, pipe); @@ -3291,7 +3283,6 @@ static void haswell_crtc_enable(struct drm_crtc *crtc) struct intel_encoder *encoder; int pipe = intel_crtc->pipe; int plane = intel_crtc->plane; - u32 temp; bool is_pch_port; WARN_ON(!crtc->enabled); @@ -3302,12 +3293,6 @@ static void haswell_crtc_enable(struct drm_crtc *crtc) intel_crtc->active = true; intel_update_watermarks(dev); - if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { - temp = I915_READ(PCH_LVDS); - if ((temp & LVDS_PORT_EN) == 0) - I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN); - } - is_pch_port = intel_crtc_driving_pch(crtc); if (is_pch_port) { @@ -3321,12 +3306,10 @@ static void haswell_crtc_enable(struct drm_crtc *crtc) if (encoder->pre_enable) encoder->pre_enable(encoder); - if (IS_HASWELL(dev)) - intel_ddi_enable_pipe_clock(intel_crtc); + intel_ddi_enable_pipe_clock(intel_crtc); - /* Enable panel fitting for LVDS */ - if (dev_priv->pch_pf_size && - (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) { + /* Enable panel fitting for eDP */ + if (dev_priv->pch_pf_size && HAS_eDP) { /* Force use of hard-coded filter coefficients * as some pre-programmed values are broken, * e.g. x201. @@ -3342,10 +3325,8 @@ static void haswell_crtc_enable(struct drm_crtc *crtc) */ intel_crtc_load_lut(crtc); - if (IS_HASWELL(dev)) { - intel_ddi_set_pipe_settings(crtc); - intel_ddi_enable_pipe_func(crtc); - } + intel_ddi_set_pipe_settings(crtc); + intel_ddi_enable_pipe_func(crtc); intel_enable_pipe(dev_priv, pipe, is_pch_port); intel_enable_plane(dev_priv, plane, pipe); @@ -3362,9 +3343,6 @@ static void haswell_crtc_enable(struct drm_crtc *crtc) for_each_encoder_on_crtc(dev, crtc, encoder) encoder->enable(encoder); - if (HAS_PCH_CPT(dev)) - intel_cpt_verify_modeset(dev, intel_crtc->pipe); - /* * There seems to be a race in PCH platform hw (at least on some * outputs) where an enabled pipe still completes any pageflip right @@ -3404,16 +3382,10 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc) intel_disable_pipe(dev_priv, pipe); - if (IS_HASWELL(dev)) - intel_ddi_disable_pipe_func(dev_priv, pipe); - /* Disable PF */ I915_WRITE(PF_CTL(pipe), 0); I915_WRITE(PF_WIN_SZ(pipe), 0); - if (IS_HASWELL(dev)) - intel_ddi_disable_pipe_clock(intel_crtc); - for_each_encoder_on_crtc(dev, crtc, encoder) if (encoder->post_disable) encoder->post_disable(encoder); @@ -3470,8 +3442,6 @@ static void haswell_crtc_disable(struct drm_crtc *crtc) struct intel_encoder *encoder; int pipe = intel_crtc->pipe; int plane = intel_crtc->plane; - u32 reg, temp; - if (!intel_crtc->active) return; @@ -3490,15 +3460,13 @@ static void haswell_crtc_disable(struct drm_crtc *crtc) intel_disable_pipe(dev_priv, pipe); - if (IS_HASWELL(dev)) - intel_ddi_disable_pipe_func(dev_priv, pipe); + intel_ddi_disable_pipe_func(dev_priv, pipe); /* Disable PF */ I915_WRITE(PF_CTL(pipe), 0); I915_WRITE(PF_WIN_SZ(pipe), 0); - if (IS_HASWELL(dev)) - intel_ddi_disable_pipe_clock(intel_crtc); + intel_ddi_disable_pipe_clock(intel_crtc); for_each_encoder_on_crtc(dev, crtc, encoder) if (encoder->post_disable) @@ -3508,33 +3476,6 @@ static void haswell_crtc_disable(struct drm_crtc *crtc) intel_disable_transcoder(dev_priv, pipe); - if (HAS_PCH_CPT(dev)) { - /* disable TRANS_DP_CTL */ - reg = TRANS_DP_CTL(pipe); - temp = I915_READ(reg); - temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK); - temp |= TRANS_DP_PORT_SEL_NONE; - I915_WRITE(reg, temp); - - /* disable DPLL_SEL */ - temp = I915_READ(PCH_DPLL_SEL); - switch (pipe) { - case 0: - temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL); - break; - case 1: - temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL); - break; - case 2: - /* C shares PLL A or B */ - temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL); - break; - default: - BUG(); /* wtf */ - } - I915_WRITE(PCH_DPLL_SEL, temp); - } - /* disable PCH DPLL */ intel_disable_pch_pll(intel_crtc);