From patchwork Tue Oct 30 11:16:34 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhenyu Wang X-Patchwork-Id: 1669141 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id 06F413FDDA for ; Tue, 30 Oct 2012 09:08:53 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C74A79ED79 for ; Tue, 30 Oct 2012 02:08:52 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id 211F99E76D for ; Mon, 29 Oct 2012 20:17:14 -0700 (PDT) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP; 29 Oct 2012 20:17:13 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.80,676,1344236400"; d="scan'208";a="241749903" Received: from debian-ivb.sh.intel.com (HELO localhost.localdomain) ([10.239.13.50]) by fmsmga002.fm.intel.com with ESMTP; 29 Oct 2012 20:17:12 -0700 From: Zhenyu Wang To: intel-gfx@lists.freedesktop.org Date: Tue, 30 Oct 2012 19:16:34 +0800 Message-Id: <1351595794-4378-1-git-send-email-zhenyuw@linux.intel.com> X-Mailer: git-send-email 1.5.3.7 Subject: [Intel-gfx] [PATCH] drm/i915: Fix HSW power well control state read X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Fix power well control state by reading real register offset. Signed-off-by: Zhenyu Wang --- drivers/gpu/drm/i915/intel_pm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 838d67d..3bcaad6 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3812,7 +3812,7 @@ void intel_init_power_wells(struct drm_device *dev) if ((well & HSW_PWR_WELL_STATE) == 0) { I915_WRITE(power_wells[i], well & HSW_PWR_WELL_ENABLE); - if (wait_for(I915_READ(power_wells[i] & HSW_PWR_WELL_STATE), 20)) + if (wait_for((I915_READ(power_wells[i]) & HSW_PWR_WELL_STATE), 20)) DRM_ERROR("Error enabling power well %lx\n", power_wells[i]); } }