From patchwork Wed Dec 12 16:15:54 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 1868681 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id 1DBFE3FC81 for ; Wed, 12 Dec 2012 17:12:59 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 23284E643D for ; Wed, 12 Dec 2012 09:12:59 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id ED8BFE5CE7; Wed, 12 Dec 2012 08:18:54 -0800 (PST) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP; 12 Dec 2012 08:18:54 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.84,267,1355126400"; d="scan'208";a="263032141" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.168]) by fmsmga002.fm.intel.com with SMTP; 12 Dec 2012 08:18:32 -0800 Received: by stinkbox (sSMTP sendmail emulation); Wed, 12 Dec 2012 18:18:31 +0200 From: ville.syrjala@linux.intel.com To: dri-devel@lists.freedesktop.org Date: Wed, 12 Dec 2012 18:15:54 +0200 Message-Id: <1355329008-31459-28-git-send-email-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 1.7.8.6 In-Reply-To: <1355329008-31459-1-git-send-email-ville.syrjala@linux.intel.com> References: <1355329008-31459-1-git-send-email-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Cc: intel-gfx@lists.freedesktop.org Subject: [Intel-gfx] [PATCH 27/81] drm/i915: Pull intel_pipe_set_base() out of the crtc_mode_set() functions X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org From: Ville Syrjälä intel_pipe_set_base() (un)pins the buffers, so it can't be called from the atomic modeset paths. Pull the intel_pipe_set_base() and watermark modifications out of i9xx_crtc_mode_set() and ironlake_crtc_mode_set() into intel_crtc_mode_set(), so that the former two can be used from the atomic modeset paths. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_display.c | 35 ++++++++++++--------------------- 1 files changed, 13 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index a184b70..6522e1e 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -4630,7 +4630,6 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc, u32 dspcntr, pipeconf; bool ok, has_reduced_clock = false; bool is_dp = false; - int ret; ok = i9xx_compute_clocks(crtc, adjusted_mode, &clock, &has_reduced_clock, &reduced_clock, @@ -4738,11 +4737,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc, I915_WRITE(DSPCNTR(plane), dspcntr); POSTING_READ(DSPCNTR(plane)); - ret = intel_pipe_set_base(crtc, x, y, fb); - - intel_update_watermarks(dev); - - return ret; + return 0; } static void ironlake_init_pch_refclk(struct drm_device *dev) @@ -5479,7 +5474,6 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc, bool ok, has_reduced_clock = false; bool is_lvds = false, is_dp = false, is_cpu_edp = false; struct intel_encoder *encoder; - int ret; bool dither, fdi_config_ok; for_each_encoder_on_crtc(dev, crtc, encoder) { @@ -5590,13 +5584,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc, I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE); POSTING_READ(DSPCNTR(plane)); - ret = intel_pipe_set_base(crtc, x, y, fb); - - intel_update_watermarks(dev); - - intel_update_linetime_watermarks(dev, pipe, adjusted_mode); - - return fdi_config_ok ? ret : -EINVAL; + return fdi_config_ok ? 0 : -EINVAL; } static int haswell_crtc_mode_set(struct drm_crtc *crtc, @@ -5613,7 +5601,6 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc, int num_connectors = 0; bool is_dp = false, is_cpu_edp = false; struct intel_encoder *encoder; - int ret; bool dither; for_each_encoder_on_crtc(dev, crtc, encoder) { @@ -5677,13 +5664,7 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc, I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE); POSTING_READ(DSPCNTR(plane)); - ret = intel_pipe_set_base(crtc, x, y, fb); - - intel_update_watermarks(dev); - - intel_update_linetime_watermarks(dev, pipe, adjusted_mode); - - return ret; + return 0; } int intel_check_clock(struct drm_crtc *crtc, @@ -5738,6 +5719,16 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc, ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode, x, y, fb); + + if (!ret) { + ret = intel_pipe_set_base(crtc, x, y, fb); + + intel_update_watermarks(dev); + + if (HAS_PCH_SPLIT(dev)) + intel_update_linetime_watermarks(dev, pipe, adjusted_mode); + } + drm_vblank_post_modeset(dev, pipe); if (ret != 0)