From patchwork Thu Dec 13 15:47:47 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhenyu Wang X-Patchwork-Id: 1871471 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id EB0343FC64 for ; Thu, 13 Dec 2012 07:50:58 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A252DE675A for ; Wed, 12 Dec 2012 23:50:58 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id 8E12EE5DB3 for ; Wed, 12 Dec 2012 23:50:49 -0800 (PST) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga101.jf.intel.com with ESMTP; 12 Dec 2012 23:50:49 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.84,273,1355126400"; d="scan'208,223";a="233284632" Received: from debian-ivb.sh.intel.com ([10.239.13.116]) by orsmga001.jf.intel.com with ESMTP; 12 Dec 2012 23:50:48 -0800 From: Zhenyu Wang To: intel-gfx@lists.freedesktop.org Date: Thu, 13 Dec 2012 23:47:47 +0800 Message-Id: <1355413667-9343-1-git-send-email-zhenyuw@linux.intel.com> X-Mailer: git-send-email 1.7.10.4 Subject: [Intel-gfx] [PATCH] drm/i915: Fix missed needs_dmar setting X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org From Ben's AGP dependence removal change, "needs_dmar" flag has not been properly setup for new chips using new GTT init function. This one adds missed setting of that flag to make sure we do pci mappings with IOMMU enabled. Signed-off-by: Zhenyu Wang --- drivers/gpu/drm/i915/i915_gem_gtt.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index cc1be53..9ae588a 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -665,6 +665,10 @@ int i915_gem_gtt_init(struct drm_device *dev) if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40))) pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40)); +#ifdef CONFIG_INTEL_IOMMU + dev_priv->mm.gtt->needs_dmar = 1; +#endif + /* For GEN6+ the PTEs for the ggtt live at 2MB + BAR0 */ gtt_bus_addr = pci_resource_start(dev->pdev, 0) + (2<<20); dev_priv->mm.gtt->gma_bus_addr = pci_resource_start(dev->pdev, 2);