From patchwork Tue Dec 18 21:42:25 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rodrigo Vivi X-Patchwork-Id: 1893761 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork2.kernel.org (Postfix) with ESMTP id A0F20DF2F6 for ; Tue, 18 Dec 2012 21:46:58 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9045BE6248 for ; Tue, 18 Dec 2012 13:46:58 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-yh0-f46.google.com (mail-yh0-f46.google.com [209.85.213.46]) by gabe.freedesktop.org (Postfix) with ESMTP id 94B3EE5D26 for ; Tue, 18 Dec 2012 13:46:48 -0800 (PST) Received: by mail-yh0-f46.google.com with SMTP id m54so303493yhm.33 for ; Tue, 18 Dec 2012 13:46:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer; bh=q/F4XjBMWLq0SIY9JXBs2LYFQNqebcbhamZQRTzXw/Q=; b=GXnNW45NHzXCdjvcHuE5yFoFjVbcwcfXsTxngC6hdXc47rLYNX39o4DPMPXZWJkulO R0v6fVDkkImjeoKjlDVyxd8y71XoeTjoLTmLISu3CcO4AdnbxXkNlnVf5BqttE+XKkMD Mnpd51efygMKjtrh9hzbc1JZcDTcjy3fwgViVKaS/AJrS5umEtfoKVXPJDeOskiS8p1j GOzfvRIUjMKr5HcNIcIDwiMag/35Loq0K4rRFsEUP+e2CI79BMNpTsvdIHy0B/n7wP8G UxemCFU+YtaoQ5wRaqelaBEt6V9bFPQW93stRbRXXvsZq1ve151oAjruGLVcOsFwjn+e 0vhw== X-Received: by 10.100.76.7 with SMTP id y7mr968944ana.61.1355867207927; Tue, 18 Dec 2012 13:46:47 -0800 (PST) Received: from manamana.ajato.com.br ([201.20.209.220]) by mx.google.com with ESMTPS id y9sm2493907anh.20.2012.12.18.13.46.45 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 18 Dec 2012 13:46:46 -0800 (PST) From: Rodrigo Vivi To: intel-gfx@lists.freedesktop.org Date: Tue, 18 Dec 2012 19:42:25 -0200 Message-Id: <1355866945-1358-1-git-send-email-rodrigo.vivi@gmail.com> X-Mailer: git-send-email 1.7.11.7 Subject: [Intel-gfx] [PATCH] drm/i915: Implement VGA request stall workarounds X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org According to BSpec, for ILK and SNB those bits must be programmed to 1 before enabling VGA display and kept enable while VGA display is enabled. It says also it is safe to have it as 1 even when VGA display is disabled. Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/i915_reg.h | 2 ++ drivers/gpu/drm/i915/intel_pm.c | 8 ++++++++ 2 files changed, 10 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index f2a5ea6..8314124 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -816,6 +816,8 @@ #define ILK_FBC_RT_VALID (1<<0) #define ILK_DISPLAY_CHICKEN1 0x42000 +#define ILK_VRD_REQ_STALL_DIS (1<<31) +#define ILK_VRD_REQ_STALL_TH (1<<29) #define ILK_FBCQ_DIS (1<<22) #define ILK_PABSTRETCH_DIS (1<<21) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index abfff29..dfb1be7 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3381,6 +3381,10 @@ static void ironlake_init_clock_gating(struct drm_device *dev) struct drm_i915_private *dev_priv = dev->dev_private; uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; + I915_WRITE(ILK_DISPLAY_CHICKEN1, + I915_READ(ILK_DISPLAY_CHICKEN1) | + ILK_VRD_REQ_STALL_DIS | ILK_VRD_REQ_STALL_TH); + /* Required for FBC */ dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE | ILK_DPFCUNIT_CLOCK_GATE_DISABLE | @@ -3470,6 +3474,10 @@ static void gen6_init_clock_gating(struct drm_device *dev) I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); + I915_WRITE(ILK_DISPLAY_CHICKEN1, + I915_READ(ILK_DISPLAY_CHICKEN1) | + ILK_VRD_REQ_STALL_DIS | ILK_VRD_REQ_STALL_TH); + I915_WRITE(ILK_DISPLAY_CHICKEN2, I915_READ(ILK_DISPLAY_CHICKEN2) | ILK_ELPIN_409_SELECT);