From patchwork Wed Jan 9 15:18:16 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 1953331 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork2.kernel.org (Postfix) with ESMTP id EB890DF215 for ; Wed, 9 Jan 2013 15:18:46 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E0AA5E663F for ; Wed, 9 Jan 2013 07:18:46 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga14.intel.com (mga14.intel.com [143.182.124.37]) by gabe.freedesktop.org (Postfix) with ESMTP id C109EE64CD for ; Wed, 9 Jan 2013 07:18:36 -0800 (PST) Received: from azsmga001.ch.intel.com ([10.2.17.19]) by azsmga102.ch.intel.com with ESMTP; 09 Jan 2013 07:18:35 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.84,438,1355126400"; d="scan'208";a="241832164" Received: from unknown (HELO localhost) ([10.252.123.93]) by azsmga001.ch.intel.com with ESMTP; 09 Jan 2013 07:18:33 -0800 From: Imre Deak To: intel-gfx@lists.freedesktop.org Date: Wed, 9 Jan 2013 17:18:16 +0200 Message-Id: <1357744696-25658-1-git-send-email-imre.deak@intel.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1357588059-6631-6-git-send-email-imre.deak@intel.com> References: <1357588059-6631-6-git-send-email-imre.deak@intel.com> Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH v3 5/7] drm/i915: reject tiling for objects smaller than their tile row size X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org For these objects there isn't enough backing storage even for a single linear pixel line, so asking tiling for them is clearly a programming error. i915_gem_get_tile_row_size() will be used by a later patch, so export it. In v3: - don't use PAGE_SIZE for the tile size as this is only coincidental and for Gen2 not even true (Chris Wilson) - use the correct tile size of 2048 bytes for Gen2 (Chris Wilson, Daniel Vetter) Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/i915_drv.h | 4 ++++ drivers/gpu/drm/i915/i915_gem.c | 8 ++++++++ drivers/gpu/drm/i915/i915_gem_tiling.c | 3 +++ 3 files changed, 15 insertions(+) [ Sending v3 only for this patch, as the rest of the patchset is unchanged. ] diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index c863b0f..e67332f 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1570,6 +1570,10 @@ i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode); uint32_t i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, int tiling_mode, bool fenced); + +size_t +i915_gem_get_tile_row_size(struct drm_device *dev, int tiling_mode, int stride); + int i915_gem_get_tile_width(struct drm_device *dev, int tiling_mode); int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index d029e9e..dd185b4 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -1447,6 +1447,14 @@ i915_gem_get_tile_width(struct drm_device *dev, int tiling_mode) return 512; } +size_t +i915_gem_get_tile_row_size(struct drm_device *dev, int tiling_mode, int stride) +{ + size_t tile_size = IS_GEN2(dev) ? 2048 : 4096; + + return stride / i915_gem_get_tile_width(dev, tiling_mode) * tile_size; +} + uint32_t i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) { diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c index e2f2a71..1a03e41 100644 --- a/drivers/gpu/drm/i915/i915_gem_tiling.c +++ b/drivers/gpu/drm/i915/i915_gem_tiling.c @@ -229,6 +229,9 @@ i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode) } } + if (size < i915_gem_get_tile_row_size(dev, tiling_mode, stride)) + return false; + tile_width = i915_gem_get_tile_width(dev, tiling_mode); /* 965+ just needs multiples of tile width */