From patchwork Mon Feb 4 15:28:02 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lespiau, Damien" X-Patchwork-Id: 2093571 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork2.kernel.org (Postfix) with ESMTP id A9AB6DFE82 for ; Mon, 4 Feb 2013 16:04:20 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 94EFAE5DC7 for ; Mon, 4 Feb 2013 08:04:20 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id 47134E60E0 for ; Mon, 4 Feb 2013 07:30:18 -0800 (PST) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga102.jf.intel.com with ESMTP; 04 Feb 2013 07:29:03 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.84,600,1355126400"; d="scan'208";a="257442339" Received: from unknown (HELO dyon.amr.corp.intel.com) ([10.255.12.132]) by orsmga001.jf.intel.com with ESMTP; 04 Feb 2013 07:30:07 -0800 From: Damien Lespiau To: intel-gfx@lists.freedesktop.org Date: Mon, 4 Feb 2013 15:28:02 +0000 Message-Id: <1359991705-5254-68-git-send-email-damien.lespiau@intel.com> X-Mailer: git-send-email 1.7.7.5 In-Reply-To: <1359991705-5254-1-git-send-email-damien.lespiau@intel.com> References: <1359991705-5254-1-git-send-email-damien.lespiau@intel.com> Subject: [Intel-gfx] [PATCH 67/90] assembler: Use brw_set_src1() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Everything is now aligned to be able to use brw_set_src1() in the opcode generation, so use it. Signed-off-by: Damien Lespiau --- assembler/gram.y | 54 +++++------------------------------------------------- 1 files changed, 5 insertions(+), 49 deletions(-) diff --git a/assembler/gram.y b/assembler/gram.y index c86e28f..8d81a04 100644 --- a/assembler/gram.y +++ b/assembler/gram.y @@ -2981,55 +2981,11 @@ static int set_instruction_src1(struct brw_instruction *instr, if (!validate_src_reg(instr, src->reg, location)) return 1; - instr->bits1.da1.src1_reg_file = src->reg.file; - instr->bits1.da1.src1_reg_type = src->reg.type; - if (src->reg.file == BRW_IMMEDIATE_VALUE) { - instr->bits3.ud = src->reg.dw1.ud; - } else if (src->reg.address_mode == BRW_ADDRESS_DIRECT) { - if (instr->header.access_mode == BRW_ALIGN_1) { - instr->bits3.da1.src1_subreg_nr = get_subreg_address(src->reg.file, src->reg.type, src->reg.subnr, src->reg.address_mode); - instr->bits3.da1.src1_reg_nr = src->reg.nr; - instr->bits3.da1.src1_vert_stride = src->reg.vstride; - instr->bits3.da1.src1_width = src->reg.width; - instr->bits3.da1.src1_horiz_stride = src->reg.hstride; - instr->bits3.da1.src1_negate = src->reg.negate; - instr->bits3.da1.src1_abs = src->reg.abs; - instr->bits3.da1.src1_address_mode = src->reg.address_mode; - } else { - instr->bits3.da16.src1_subreg_nr = get_subreg_address(src->reg.file, src->reg.type, src->reg.subnr, src->reg.address_mode); - instr->bits3.da16.src1_reg_nr = src->reg.nr; - instr->bits3.da16.src1_vert_stride = src->reg.vstride; - instr->bits3.da16.src1_negate = src->reg.negate; - instr->bits3.da16.src1_abs = src->reg.abs; - instr->bits3.da16.src1_swz_x = BRW_GET_SWZ(SWIZZLE(src->reg), 0); - instr->bits3.da16.src1_swz_y = BRW_GET_SWZ(SWIZZLE(src->reg), 1); - instr->bits3.da16.src1_swz_z = BRW_GET_SWZ(SWIZZLE(src->reg), 2); - instr->bits3.da16.src1_swz_w = BRW_GET_SWZ(SWIZZLE(src->reg), 3); - instr->bits3.da16.src1_address_mode = src->reg.address_mode; - } - } else { - if (instr->header.access_mode == BRW_ALIGN_1) { - instr->bits3.ia1.src1_indirect_offset = src->reg.dw1.bits.indirect_offset; - instr->bits3.ia1.src1_subreg_nr = get_indirect_subreg_address(src->reg.subnr); - instr->bits3.ia1.src1_abs = src->reg.abs; - instr->bits3.ia1.src1_negate = src->reg.negate; - instr->bits3.ia1.src1_address_mode = src->reg.address_mode; - instr->bits3.ia1.src1_horiz_stride = src->reg.hstride; - instr->bits3.ia1.src1_width = src->reg.width; - instr->bits3.ia1.src1_vert_stride = src->reg.vstride; - } else { - instr->bits3.ia16.src1_swz_x = BRW_GET_SWZ(SWIZZLE(src->reg), 0); - instr->bits3.ia16.src1_swz_y = BRW_GET_SWZ(SWIZZLE(src->reg), 1); - instr->bits3.ia16.src1_swz_z = BRW_GET_SWZ(SWIZZLE(src->reg), 2); - instr->bits3.ia16.src1_swz_w = BRW_GET_SWZ(SWIZZLE(src->reg), 3); - instr->bits3.ia16.src1_indirect_offset = (src->reg.dw1.bits.indirect_offset >> 4); /* half register aligned */ - instr->bits3.ia16.src1_subreg_nr = get_indirect_subreg_address(src->reg.subnr); - instr->bits3.ia16.src1_abs = src->reg.abs; - instr->bits3.ia16.src1_negate = src->reg.negate; - instr->bits3.ia16.src1_address_mode = src->reg.address_mode; - instr->bits3.ia16.src1_vert_stride = src->reg.vstride; - } - } + /* the assembler support expressing subnr in bytes or in number of + * elements. */ + resolve_subnr(&src->reg); + + brw_set_src1(&genasm_compile, instr, src->reg); return 0; }