From patchwork Mon Feb 4 15:27:01 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lespiau, Damien" X-Patchwork-Id: 2092611 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork2.kernel.org (Postfix) with ESMTP id C3B31DFE82 for ; Mon, 4 Feb 2013 15:32:39 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B609FE5F02 for ; Mon, 4 Feb 2013 07:32:39 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id EA79DE5FBF for ; Mon, 4 Feb 2013 07:28:59 -0800 (PST) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga102.jf.intel.com with ESMTP; 04 Feb 2013 07:27:44 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.84,600,1355126400"; d="scan'208";a="257441530" Received: from unknown (HELO dyon.amr.corp.intel.com) ([10.255.12.132]) by orsmga001.jf.intel.com with ESMTP; 04 Feb 2013 07:28:55 -0800 From: Damien Lespiau To: intel-gfx@lists.freedesktop.org Date: Mon, 4 Feb 2013 15:27:01 +0000 Message-Id: <1359991705-5254-7-git-send-email-damien.lespiau@intel.com> X-Mailer: git-send-email 1.7.7.5 In-Reply-To: <1359991705-5254-1-git-send-email-damien.lespiau@intel.com> References: <1359991705-5254-1-git-send-email-damien.lespiau@intel.com> Subject: [Intel-gfx] [PATCH 06/90] assembler: Sync brw_instruction's header with mesa's X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Two changes there, a field has been renamed and one bit of padding is now used for compressed instructions. Signed-off-by: Damien Lespiau --- assembler/brw_structs.h | 34 +++++++++++++++++++--------------- assembler/disasm.c | 8 ++++---- assembler/gram.y | 30 +++++++++++++++--------------- 3 files changed, 38 insertions(+), 34 deletions(-) diff --git a/assembler/brw_structs.h b/assembler/brw_structs.h index 3a3b160..59b28fa 100644 --- a/assembler/brw_structs.h +++ b/assembler/brw_structs.h @@ -1043,21 +1043,25 @@ struct brw_instruction { struct { - GLuint opcode:7; /* 0x0000007f */ - GLuint pad:1; /* 0x00000080 */ /* reserved for Opcode */ - GLuint access_mode:1; /* 0x00000100 */ - GLuint mask_control:1; /* 0x00000200 */ - GLuint dependency_control:2; /* 0x00000c00 */ - GLuint compression_control:2; /* 0x00003000 */ - GLuint thread_control:2; /* 0x0000c000 */ - GLuint predicate_control:4; /* 0x000f0000 */ - GLuint predicate_inverse:1; /* 0x00100000 */ - GLuint execution_size:3; /* 0x00e00000 */ - GLuint sfid_destreg__conditionalmod:4; /* sfid - send on GEN6+, destreg - send on Prev GEN6, conditionalmod - others */ - GLuint acc_wr_control:1; /* 0x10000000 */ - GLuint pad0:1; /* 0x20000000 */ - GLuint debug_control:1; /* 0x40000000 */ - GLuint saturate:1; /* 0x80000000 */ + GLuint opcode:7; + GLuint pad:1; + GLuint access_mode:1; + GLuint mask_control:1; + GLuint dependency_control:2; + GLuint compression_control:2; /* gen6: quater control */ + GLuint thread_control:2; + GLuint predicate_control:4; + GLuint predicate_inverse:1; + GLuint execution_size:3; + /** + * Conditional Modifier for most instructions. On Gen6+, this is also + * used for the SEND instruction's Message Target/SFID. + */ + GLuint destreg__conditionalmod:4; + GLuint acc_wr_control:1; + GLuint cmpt_control:1; + GLuint debug_control:1; + GLuint saturate:1; } header; union { diff --git a/assembler/disasm.c b/assembler/disasm.c index 1ec6ae5..1cb0924 100644 --- a/assembler/disasm.c +++ b/assembler/disasm.c @@ -798,7 +798,7 @@ int disasm (FILE *file, struct brw_instruction *inst) if (inst->header.opcode != BRW_OPCODE_SEND && inst->header.opcode != BRW_OPCODE_SENDC) err |= control (file, "conditional modifier", conditional_modifier, - inst->header.sfid_destreg__conditionalmod, NULL); + inst->header.destreg__conditionalmod, NULL); if (inst->header.opcode != BRW_OPCODE_NOP) { string (file, "("); @@ -808,7 +808,7 @@ int disasm (FILE *file, struct brw_instruction *inst) if (inst->header.opcode == BRW_OPCODE_SEND || inst->header.opcode == BRW_OPCODE_SENDC) - format (file, " %d", inst->header.sfid_destreg__conditionalmod); + format (file, " %d", inst->header.destreg__conditionalmod); if (opcode[inst->header.opcode].ndst > 0) { pad (file, 16); @@ -829,8 +829,8 @@ int disasm (FILE *file, struct brw_instruction *inst) pad (file, 16); space = 0; err |= control (file, "target function", target_function, - inst->header.sfid_destreg__conditionalmod, &space); - switch (inst->header.sfid_destreg__conditionalmod) { + inst->header.destreg__conditionalmod, &space); + switch (inst->header.destreg__conditionalmod) { case BRW_MESSAGE_TARGET_MATH: err |= control (file, "math function", math_function, inst->bits3.math.function, &space); diff --git a/assembler/gram.y b/assembler/gram.y index 2ed79c1..a762835 100644 --- a/assembler/gram.y +++ b/assembler/gram.y @@ -678,7 +678,7 @@ unaryinstruction: { memset(&$$, 0, sizeof($$)); $$.header.opcode = $2; - $$.header.sfid_destreg__conditionalmod = $3.cond; + $$.header.destreg__conditionalmod = $3.cond; $$.header.saturate = $4; $$.header.execution_size = $5; set_instruction_options(&$$, &$8); @@ -715,7 +715,7 @@ binaryinstruction: { memset(&$$, 0, sizeof($$)); $$.header.opcode = $2; - $$.header.sfid_destreg__conditionalmod = $3.cond; + $$.header.destreg__conditionalmod = $3.cond; $$.header.saturate = $4; $$.header.execution_size = $5; set_instruction_options(&$$, &$9); @@ -754,7 +754,7 @@ binaryaccinstruction: { memset(&$$, 0, sizeof($$)); $$.header.opcode = $2; - $$.header.sfid_destreg__conditionalmod = $3.cond; + $$.header.destreg__conditionalmod = $3.cond; $$.header.saturate = $4; $$.header.execution_size = $5; set_instruction_options(&$$, &$9); @@ -801,7 +801,7 @@ trinaryinstruction: $$.bits1.three_src_gen6.flag_subreg_nr = $1.bits2.da1.flag_subreg_nr; $$.header.opcode = $2; - $$.header.sfid_destreg__conditionalmod = $3.cond; + $$.header.destreg__conditionalmod = $3.cond; $$.header.saturate = $4; $$.header.execution_size = $5; @@ -839,7 +839,7 @@ sendinstruction: predicate SEND execsize exp post_dst payload msgtarget memset(&$$, 0, sizeof($$)); $$.header.opcode = $2; $$.header.execution_size = $3; - $$.header.sfid_destreg__conditionalmod = $4; /* msg reg index */ + $$.header.destreg__conditionalmod = $4; /* msg reg index */ set_instruction_predicate(&$$, &$1); if (set_instruction_dest(&$$, &$5) != 0) YYERROR; @@ -869,9 +869,9 @@ sendinstruction: predicate SEND execsize exp post_dst payload msgtarget if (IS_GENp(5)) { if (IS_GENp(6)) { - $$.header.sfid_destreg__conditionalmod = $7.bits2.send_gen5.sfid; + $$.header.destreg__conditionalmod = $7.bits2.send_gen5.sfid; } else { - $$.header.sfid_destreg__conditionalmod = $4; /* msg reg index */ + $$.header.destreg__conditionalmod = $4; /* msg reg index */ $$.bits2.send_gen5.sfid = $7.bits2.send_gen5.sfid; $$.bits2.send_gen5.end_of_thread = $12.bits3.generic_gen5.end_of_thread; } @@ -882,7 +882,7 @@ sendinstruction: predicate SEND execsize exp post_dst payload msgtarget $$.bits3.generic_gen5.end_of_thread = $12.bits3.generic_gen5.end_of_thread; } else { - $$.header.sfid_destreg__conditionalmod = $4; /* msg reg index */ + $$.header.destreg__conditionalmod = $4; /* msg reg index */ $$.bits3.generic = $7.bits3.generic; $$.bits3.generic.msg_length = $9; $$.bits3.generic.response_length = $11; @@ -895,7 +895,7 @@ sendinstruction: predicate SEND execsize exp post_dst payload msgtarget memset(&$$, 0, sizeof($$)); $$.header.opcode = $2; $$.header.execution_size = $3; - $$.header.sfid_destreg__conditionalmod = $5.reg_nr; /* msg reg index */ + $$.header.destreg__conditionalmod = $5.reg_nr; /* msg reg index */ set_instruction_predicate(&$$, &$1); @@ -918,7 +918,7 @@ sendinstruction: predicate SEND execsize exp post_dst payload msgtarget memset(&$$, 0, sizeof($$)); $$.header.opcode = $2; $$.header.execution_size = $3; - $$.header.sfid_destreg__conditionalmod = $5.reg_nr; /* msg reg index */ + $$.header.destreg__conditionalmod = $5.reg_nr; /* msg reg index */ set_instruction_predicate(&$$, &$1); if (set_instruction_dest(&$$, &$4) != 0) @@ -948,7 +948,7 @@ sendinstruction: predicate SEND execsize exp post_dst payload msgtarget memset(&$$, 0, sizeof($$)); $$.header.opcode = $2; $$.header.execution_size = $3; - $$.header.sfid_destreg__conditionalmod = ($6 & EX_DESC_SFID_MASK); /* SFID */ + $$.header.destreg__conditionalmod = ($6 & EX_DESC_SFID_MASK); /* SFID */ set_instruction_predicate(&$$, &$1); if (set_instruction_dest(&$$, &$4) != 0) @@ -994,7 +994,7 @@ sendinstruction: predicate SEND execsize exp post_dst payload msgtarget memset(&$$, 0, sizeof($$)); $$.header.opcode = $2; $$.header.execution_size = $3; - $$.header.sfid_destreg__conditionalmod = ($6 & EX_DESC_SFID_MASK); /* SFID */ + $$.header.destreg__conditionalmod = ($6 & EX_DESC_SFID_MASK); /* SFID */ set_instruction_predicate(&$$, &$1); if (set_instruction_dest(&$$, &$4) != 0) @@ -1029,7 +1029,7 @@ sendinstruction: predicate SEND execsize exp post_dst payload msgtarget memset(&$$, 0, sizeof($$)); $$.header.opcode = $2; $$.header.execution_size = $3; - $$.header.sfid_destreg__conditionalmod = $5.reg_nr; /* msg reg index */ + $$.header.destreg__conditionalmod = $5.reg_nr; /* msg reg index */ set_instruction_predicate(&$$, &$1); if (set_instruction_dest(&$$, &$4) != 0) @@ -1051,7 +1051,7 @@ sendinstruction: predicate SEND execsize exp post_dst payload msgtarget memset(&$$, 0, sizeof($$)); $$.header.opcode = $2; $$.header.execution_size = $3; - $$.header.sfid_destreg__conditionalmod = $5.reg_nr; /* msg reg index */ + $$.header.destreg__conditionalmod = $5.reg_nr; /* msg reg index */ set_instruction_predicate(&$$, &$1); @@ -1100,7 +1100,7 @@ mathinstruction: predicate MATH_INST execsize dst src srcimm math_function insto { memset(&$$, 0, sizeof($$)); $$.header.opcode = $2; - $$.header.sfid_destreg__conditionalmod = $7; + $$.header.destreg__conditionalmod = $7; $$.header.execution_size = $3; set_instruction_options(&$$, &$8); set_instruction_predicate(&$$, &$1);